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Searched refs:buildPtrAdd (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DGISelAliasTest.cpp32 auto Addr = B.buildPtrAdd(P0, Base, B.buildConstant(S64, 8)); in TEST_F()
33 auto Addr2 = B.buildPtrAdd(P0, Base, B.buildConstant(S64, 8)); in TEST_F()
82 auto Addr = B.buildPtrAdd(P0, Base, B.buildConstant(S64, 8)); in TEST_F()
83 auto Addr2 = B.buildPtrAdd(P0, Base, B.buildConstant(S64, 16)); in TEST_F()
96 auto Addr3 = B.buildPtrAdd(P0, Base, B.buildConstant(S64, 4)); in TEST_F()
H A DPatternMatchTest.cpp211 auto PtrAdd = B.buildPtrAdd(p0, {B.buildUndef(p0)}, Copies[0]); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp379 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize); in legalizeCustom()
408 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize); in legalizeCustom()
H A DMipsCallLowering.cpp239 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
/llvm-project-15.0.7/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp63 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallLowering.cpp101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PreLegalizerCombiner.cpp219 B.buildPtrAdd( in applyFoldGlobalOffset()
H A DAArch64PostLegalizerCombiner.cpp322 auto HighPtr = B.buildPtrAdd(MRI.getType(PtrReg), PtrReg, in applySplitStoreZero128()
H A DAArch64LegalizerInfo.cpp1165 auto ListTmp = MIRBuilder.buildPtrAdd(PtrTy, List, AlignMinus1.getReg(0)); in legalizeVaArg()
1179 auto NewList = MIRBuilder.buildPtrAdd(PtrTy, DstPtr, Size.getReg(0)); in legalizeVaArg()
H A DAArch64CallLowering.cpp268 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp180 MachineInstrBuilder MachineIRBuilder::buildPtrAdd(const DstOp &Res, in buildPtrAdd() function in MachineIRBuilder
203 return buildPtrAdd(Res, Op0, Cst.getReg(0)); in materializePtrAdd()
411 auto Ptr = buildPtrAdd(PtrTy, BasePtr, ConstOffset); in buildLoadFromOffset()
H A DLegalizerHelper.cpp3038 auto SmallPtr = MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); in lowerLoad()
3150 MIRBuilder.buildPtrAdd(PtrTy, PtrReg, OffsetCst); in lowerStore()
3595 return MIRBuilder.buildPtrAdd(PtrTy, VecPtr, Mul).getReg(0); in getVectorElementPointer()
7547 Ptr = MIB.buildPtrAdd(PtrTy, Dst, Offset).getReg(0); in lowerMemset()
7689 LoadPtr = MIB.buildPtrAdd(SrcTy, Src, Offset).getReg(0); in lowerMemcpy()
7697 StorePtr = MIB.buildPtrAdd(DstTy, Dst, Offset).getReg(0); in lowerMemcpy()
7787 LoadPtr = MIB.buildPtrAdd(SrcTy, Src, Offset).getReg(0); in lowerMemmove()
7805 StorePtr = MIB.buildPtrAdd(DstTy, Dst, Offset).getReg(0); in lowerMemmove()
H A DIRTranslator.cpp1539 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, OffsetMIB.getReg(0)) in translateGetElementPtr()
1566 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0); in translateGetElementPtr()
1573 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0)); in translateGetElementPtr()
H A DCombinerHelper.cpp2075 auto PtrAdd = Builder.buildPtrAdd(PtrTy, LHS, RHS); in applyCombineAddP2IToPtrAdd()
4529 Builder.buildPtrAdd(PtrTy, Src1Reg, RHS->getOperand(1).getReg()); in matchReassocConstantInnerRHS()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp106 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp213 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); in getStackAddress()
394 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg); in lowerParameterPtr()
H A DAMDGPULegalizerInfo.cpp1881 B.buildPtrAdd(LoadAddr, KernargPtrReg, in getSegmentAperture()
1903 B.buildPtrAdd(LoadAddr, QueuePtr, in getSegmentAperture()
3400 return B.buildPtrAdd(PtrTy, KernArgReg, COffset).getReg(0); in getKernargParameterPtr()
4179 B.buildPtrAdd(DstReg, KernargPtrReg, B.buildConstant(IdxTy, Offset).getReg(0)); in getImplicitArgPtr()
5328 B.buildPtrAdd(LoadAddr, KernargPtrReg, in legalizeTrapHsaQueuePtr()
H A DAMDGPURegisterBankInfo.cpp1197 auto PtrAdd = B.buildPtrAdd(PtrTy, SPCopy, ScaledSize); in applyMappingDynStackAlloc()
1201 B.buildPtrAdd(Dst, SPCopy, ScaledSize); in applyMappingDynStackAlloc()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h462 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,