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Searched refs:buildNot (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DMachineIRBuilderTest.cpp197 B.buildNot(S64, Copies[0]); in TEST_F()
201 B.buildNot(S128, Merge); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp870 return MIB.buildNot(DstTy, FCmp).getReg(0); in getVectorFCMP()
949 CmpRes = MIB.buildNot(DstTy, CmpRes).getReg(0); in lowerVectorFCMP()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1621 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) { in buildNot() function
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp2847 auto InvShiftedMask = B.buildNot(TargetTy, ShiftedMask); in buildBitFieldInsert()
5749 Z = MIRBuilder.buildNot(ShTy, Z).getReg(0); in lowerFunnelShiftWithInverse()
5790 auto NotZ = MIRBuilder.buildNot(ShTy, Z); in lowerFunnelShiftAsShifts()
6983 Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS; in lowerAddSubSatToMinMax()
7256 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); in lowerSelect()
H A DCombinerHelper.cpp3055 auto Not = Builder.buildNot(MRI.getType(X), X); in applyXorOfAndWithSameReg()
5614 MIB.buildOr(DstReg, MIB.buildNot(OpTy, Cond), TrueReg); in matchSelectToLogical()
5622 MIB.buildAnd(DstReg, MIB.buildNot(OpTy, Cond), FalseReg); in matchSelectToLogical()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2170 auto Not = B.buildNot(S64, Shr); in legalizeIntrinsicTrunc()