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Searched refs:brtarget (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstrAliases.td67 (BCOND brtarget:$imm, condVal)>;
71 (BCONDA brtarget:$imm, condVal)>;
208 (FBCOND brtarget:$imm, condVal), 0>;
212 (FBCONDA brtarget:$imm, condVal), 0>;
216 (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
221 (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
226 (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
231 (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
236 (BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,
261 (CBCOND brtarget:$imm, condVal), 0>;
[all …]
H A DSparcInstrInfo.td185 def brtarget : Operand<OtherVT> {
859 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
909 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
912 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
949 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
952 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
972 def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
975 def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips64r6InstrInfo.td83 class BGEC64_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR64Opnd>;
84 class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>;
85 class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>;
86 class BNEC64_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR64Opnd>;
87 class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>;
88 class BLTUC64_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR64Opnd>;
89 class BLTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR64Opnd>;
90 class BGEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR64Opnd>;
91 class BLEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR64Opnd>;
92 class BGTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR64Opnd>;
H A DMips32r6InstrInfo.td420 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
435 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
436 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
437 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
438 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
440 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
441 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
453 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
464 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
475 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
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H A DMipsInstrInfo.td838 def brtarget : Operand<OtherVT> {
1999 (ins brtarget:$tgt, brtarget:$baltgt), []> {
2004 (ins brtarget:$tgt), []> {
2010 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []> {
2015 (ins GPR32Opnd:$src, brtarget:$tgt), []> {
2226 def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>,
2230 def BNEL : MMRel, CBranchLikely<"bnel", brtarget, GPR32Opnd>,
2248 def B : UncondBranch<BEQ, brtarget>, ISA_MIPS1;
2264 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd>,
2270 def BAL_BR : BAL_BR_Pseudo<BGEZAL, brtarget>, ISA_MIPS1;
[all …]
H A DMips64InstrInfo.td266 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>,
268 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>,
270 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>,
431 PseudoSE<(outs GPR64Opnd:$dst), (ins brtarget:$tgt), []>, GPR_64 {
445 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>,
512 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd,
514 def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64,
518 def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd,
520 def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64,
1072 brtarget:$offset), 0>,
[all …]
H A DMipsInstrFPU.td730 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
732 def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>,
734 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
736 def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>,
915 (BCTrue FCC0, brtarget:$offset), 1>;
918 (BCFalse FCC0, brtarget:$offset), 1>;
H A DMips16InstrInfo.td54 FI16<op, (outs), (ins brtarget:$imm16),
112 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
151 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
214 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
265 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
277 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
H A DMicroMipsInstrInfo.td1413 (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
1416 (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
H A DMipsDSPInstrInfo.td889 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget, NoItinerary>;
H A DMipsMSAInstrInfo.td1414 dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td57 def brtarget : Operand<OtherVT> {
160 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
176 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
192 (ins GPR32:$dst, GPR32:$src, brtarget:$BrDst),
208 (ins GPR32:$dst, i32imm:$imm, brtarget:$BrDst),
473 (ins brtarget:$BrDst),
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600Instructions.td1383 (ins brtarget:$target, R600_Predicate_Bit:$p),
1390 (ins brtarget:$target),
1567 (ins brtarget:$target, rci:$src0),
1571 (ins brtarget:$target, rcf:$src0),
1597 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
H A DSIInstructions.td340 (ins SReg_1:$vcc, brtarget:$target),
347 (outs SReg_1:$dst), (ins SReg_1:$vcc, brtarget:$target),
356 (ins SReg_1:$src, brtarget:$target), [], 1, 1> {
363 (ins brtarget:$target), [], 1> {
370 (outs), (ins SReg_1:$saved, brtarget:$target),
H A DAMDGPUInstructions.td165 def brtarget : Operand<OtherVT>;
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td185 def brtarget : Operand<OtherVT>;
279 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
281 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
646 def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
648 def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp4873 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; in DecodeThumb2BCCInstruction() local
4874 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; in DecodeThumb2BCCInstruction()
4875 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; in DecodeThumb2BCCInstruction()
4876 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; in DecodeThumb2BCCInstruction()
4877 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; in DecodeThumb2BCCInstruction()
4879 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) in DecodeThumb2BCCInstruction()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZOperands.td551 // Variants of brtarget for use with branch prediction preload.
/llvm-project-15.0.7/llvm/docs/
H A DWritingAnLLVMBackend.rst971 For example, the X86 backend defines ``brtarget`` and ``brtarget8``, both
977 def brtarget : Operand<OtherVT>;
988 brtarget,
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td38 def brtarget : Operand<OtherVT>;
3148 def CBranch : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
3152 def CBranchOther : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
3156 def GOTO : NVPTXInst<(outs), (ins brtarget:$target),
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td3931 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
5555 (ins GPRlr:$tc, brtarget:$target),
5565 (ins rGPR:$tc, brtarget:$target),
5573 (ins rGPR:$tc, rGPR:$elts, brtarget:$target),
5579 t2PseudoInst<(outs), (ins GPRlr:$tc, brtarget:$target),
5587 t2PseudoInst<(outs GPRlr:$Rm), (ins GPRlr:$tc, brtarget:$target),
H A DARMInstrInfo.td548 // FIXME: rename brtarget to t2_brtarget
549 def brtarget : Operand<OtherVT> {
4991 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4997 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Darm64-irtranslator.ll159 %brtarget = load i8*, i8** %arrayidx, align 8
160 indirectbr i8* %brtarget, [label %L1, label %L2]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrCompiler.td230 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
H A DX86InstrInfo.td506 def brtarget : BranchTargetOperand<OtherVT>;