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/llvm-project-15.0.7/llvm/test/MC/Mips/msa/
H A Dinvalid.s8 addvi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
9 addvi.b $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
10 addvi.h $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
11 addvi.h $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
12 addvi.w $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
13 addvi.w $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
14 addvi.d $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
15 addvi.d $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
16 andi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:22: error: expected 8-bit unsigned immediate
17 andi.b $w1, $w2, 256 # CHECK: :[[@LINE]]:22: error: expected 8-bit unsigned immediate
[all …]
H A Dinvalid-64.s10 insve.b $w25[-1], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
11 insve.b $w25[16], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
12 insve.h $w24[-1], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
13 insve.h $w24[8], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
14 insve.w $w0[-1], $w13[0] # CHECK: :[[@LINE]]:17: error: expected 2-bit unsigned immediate
15 insve.w $w0[4], $w13[0] # CHECK: :[[@LINE]]:17: error: expected 2-bit unsigned immediate
16 insve.d $w3[-1], $w18[0] # CHECK: :[[@LINE]]:17: error: expected 1-bit unsigned immediate
17 insve.d $w3[2], $w18[0] # CHECK: :[[@LINE]]:17: error: expected 1-bit unsigned immediate
24 sat_s.b $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate
25 sat_s.b $w31, $w31, 8 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate
[all …]
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DMSP430Target.def179 // With 16-bit hardware multiplier
180 MSP430_MCU_FEAT("msp430f147", "16bit")
181 MSP430_MCU_FEAT("msp430f148", "16bit")
182 MSP430_MCU_FEAT("msp430f149", "16bit")
186 MSP430_MCU_FEAT("msp430f167", "16bit")
187 MSP430_MCU_FEAT("msp430f168", "16bit")
188 MSP430_MCU_FEAT("msp430f169", "16bit")
192 MSP430_MCU_FEAT("msp430c336", "16bit")
193 MSP430_MCU_FEAT("msp430c337", "16bit")
194 MSP430_MCU_FEAT("msp430e337", "16bit")
[all …]
H A DBuiltinsRISCV.def20 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
22 TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb,64bit")
24 TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit")
38 "experimental-zbe,64bit")
42 "experimental-zbe,64bit")
86 TARGET_BUILTIN(__builtin_riscv_aes64ds_64, "WiWiWi", "nc", "zknd,64bit")
87 TARGET_BUILTIN(__builtin_riscv_aes64dsm_64, "WiWiWi", "nc", "zknd,64bit")
88 TARGET_BUILTIN(__builtin_riscv_aes64im_64, "WiWi", "nc", "zknd,64bit")
97 TARGET_BUILTIN(__builtin_riscv_aes64es_64, "WiWiWi", "nc", "zkne,64bit")
98 TARGET_BUILTIN(__builtin_riscv_aes64esm_64, "WiWiWi", "nc", "zkne,64bit")
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips/
H A Dinvalid.s7 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
8 addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
9 break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
10 break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
11 break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
12 break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
13 break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
15 break16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
16 break16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
17 cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/dsp/
H A Dinvalid.s4 extp $2, $ac1, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
5 extp $2, $ac1, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
6 extpdp $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
7 extpdp $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
8 extr.w $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
9 extr.w $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
10 extr_r.w $2, $ac1, -1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
11 extr_r.w $2, $ac1, 32 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
12 extr_rs.w $2, $ac1, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
13 extr_rs.w $2, $ac1, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dempty.td10 // CHECK: bit Empty = 1;
11 // CHECK: bit NotEmpty = 0;
13 // CHECK: bit Empty = 0;
14 // CHECK: bit NotEmpty = 1;
16 // CHECK: bit Empty = 0;
17 // CHECK: bit NotEmpty = 1;
20 bit Empty = !empty(ADag);
33 // CHECK: bit Empty = 1;
36 // CHECK: bit Empty = 0;
39 // CHECK: bit Empty = 0;
[all …]
H A Dtrue-false.td10 // CHECK: bit flag1 = 1;
11 // CHECK: bit flag2 = 0;
15 bit flag1 = true;
16 bit flag2 = false;
51 // CHECK: bit xorFF = 0;
52 // CHECK: bit xorFT = 1;
53 // CHECK: bit xorTF = 1;
54 // CHECK: bit xorTT = 0;
58 bit xorFT = !xor(false, true);
59 bit xorTF = !xor(true, false);
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td17 field bit SALU = 0;
18 field bit VALU = 0;
21 field bit SOP1 = 0;
22 field bit SOP2 = 0;
23 field bit SOPC = 0;
35 field bit DPP = 0;
43 field bit EXP = 0;
45 field bit DS = 0;
258 bit UseExec = 0, bit DefExec = 0> :
314 bit d16;
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips-dsp/
H A Dinvalid.s4 repl.ph $2, -513 # CHECK: :[[@LINE]]:15: error: expected 10-bit signed immediate
5 repl.ph $2, 512 # CHECK: :[[@LINE]]:15: error: expected 10-bit signed immediate
6 shll.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
7 shll.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
8 shll_s.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
9 shll_s.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
10 shll.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
11 shll.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
15 shra.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
24 shilo $ac1, 64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td16 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
18 def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
19 def WriteIMul32 : SchedWrite; // 32-bit multiply on RV64I
41 def WriteFALU16 : SchedWrite; // FP 16-bit computation
42 def WriteFALU32 : SchedWrite; // FP 32-bit computation
43 def WriteFALU64 : SchedWrite; // FP 64-bit computation
53 def WriteFSqrt16 : SchedWrite; // 16-bit floating point sqrt
54 def WriteFSqrt32 : SchedWrite; // 32-bit floating point sqrt
133 def ReadFALU16 : SchedRead; // FP 16-bit computation
134 def ReadFALU32 : SchedRead; // FP 32-bit computation
[all …]
/llvm-project-15.0.7/llvm/include/llvm/BinaryFormat/ELFRelocs/
H A DM68k.def6 ELF_RELOC(R_68K_32, 1) /* Direct 32 bit */
7 ELF_RELOC(R_68K_16, 2) /* Direct 16 bit */
8 ELF_RELOC(R_68K_8, 3) /* Direct 8 bit */
9 ELF_RELOC(R_68K_PC32, 4) /* PC relative 32 bit */
10 ELF_RELOC(R_68K_PC16, 5) /* PC relative 16 bit */
11 ELF_RELOC(R_68K_PC8, 6) /* PC relative 8 bit */
15 ELF_RELOC(R_68K_GOTOFF32, 10) /* 32 bit GOT offset */
16 ELF_RELOC(R_68K_GOTOFF16, 11) /* 16 bit GOT offset */
17 ELF_RELOC(R_68K_GOTOFF8, 12) /* 8 bit GOT offset */
21 ELF_RELOC(R_68K_PLTOFF32, 16) /* 32 bit PLT offset */
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/dspr2/
H A Dinvalid.s5 append $2, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
6 append $2, $3, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
7 balign $2, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
8 balign $2, $3, 4 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
9 precr_sra.ph.w $24, $25, -1 # CHECK: :[[@LINE]]:28: error: expected 5-bit unsigned immediate
15 shra.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
16 shra.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
17 shra_r.qb $3, $4, 8 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
18 shra_r.qb $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
19 shrl.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips32r6/
H A Dinvalid.s9 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
10 addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
12 align $4, $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate
13 align $4, $2, $3, 4 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate
20 break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
21 break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
22 break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
23 break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
27 cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
28 cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/cnmips/
H A Dinvalid.s8 bbit0 $19, -1, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
9 bbit0 $19, 64, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
10 bbit032 $19, -1, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
11 bbit032 $19, 32, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
12 bbit1 $19, -1, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
13 bbit1 $19, 64, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
14 bbit132 $19, -1, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
15 bbit132 $19, 32, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
16 ins $2, $3, -1, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
17 ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/eva/
H A Dinvalid.s8 cachee -1, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
9 cachee 32, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
10 prefe -1, 255($7) # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
11 prefe 32, 255($7) # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
14 lle $4, 512($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
15 lle $4, -513($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
18 lwe $4, 512($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
19 lwe $4, -513($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
22 sbe $4, 512($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
23 sbe $4, -513($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64GenRegisterBankInfo.def16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
80 // 28: FPR 16-bit value to GPR 16-bit. <-- This must match
85 // 30: FPR 32-bit value to GPR 32-bit value.
88 // 32: FPR 64-bit value to GPR 64-bit value.
91 // 34: FPR 128-bit value to GPR 128-bit value (invalid)
94 // 36: FPR 256-bit value to GPR 256-bit value (invalid)
97 // 38: FPR 512-bit value to GPR 512-bit value (invalid)
100 // 40: GPR 32-bit value to FPR 32-bit value.
[all …]
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DInstructionUtils.h36 static inline uint32_t Bit32(const uint32_t bits, const uint32_t bit) { in Bit32() argument
37 return (bits >> bit) & 1u; in Bit32()
40 static inline uint64_t Bit64(const uint64_t bits, const uint32_t bit) { in Bit64() argument
41 return (bits >> bit) & 1ull; in Bit64()
55 static inline void SetBit32(uint32_t &bits, const uint32_t bit, in SetBit32() argument
57 SetBits32(bits, bit, bit, val); in SetBit32()
73 static inline uint64_t MaskUpToBit(const uint64_t bit) { in MaskUpToBit() argument
74 if (bit >= 63) in MaskUpToBit()
76 return (1ull << (bit + 1ull)) - 1ull; in MaskUpToBit()
90 return (value & (1ull << bit)) != 0; in BitIsSet()
[all …]
/llvm-project-15.0.7/llvm/docs/PDB/
H A DTpiStream.rst138 Int16Short = 0x0011, // 16 bit signed
139 UInt16Short = 0x0021, // 16 bit unsigned
142 Int32Long = 0x0012, // 32 bit signed
143 UInt32Long = 0x0022, // 32 bit unsigned
146 Int64Quad = 0x0013, // 64 bit signed
147 UInt64Quad = 0x0023, // 64 bit unsigned
171 Boolean8 = 0x0030, // 8 bit boolean
172 Boolean16 = 0x0031, // 16 bit boolean
173 Boolean32 = 0x0032, // 32 bit boolean
174 Boolean64 = 0x0033, // 64 bit boolean
[all …]
/llvm-project-15.0.7/clang/test/SemaOpenCL/
H A Dbuiltins-amdgcn-error-f16.cl9 …uph(a, b, c); // expected-error {{'__builtin_amdgcn_div_fixuph' needs target feature 16-bit-insts}}
10 …tin_amdgcn_rcph(a); // expected-error {{'__builtin_amdgcn_rcph' needs target feature 16-bit-insts}}
11 …n_amdgcn_sqrth(a); // expected-error {{'__builtin_amdgcn_sqrth' needs target feature 16-bit-insts}}
12 …tin_amdgcn_rsqh(a); // expected-error {{'__builtin_amdgcn_rsqh' needs target feature 16-bit-insts}}
13 …tin_amdgcn_sinh(a); // expected-error {{'__builtin_amdgcn_sinh' needs target feature 16-bit-insts}}
14 …tin_amdgcn_cosh(a); // expected-error {{'__builtin_amdgcn_cosh' needs target feature 16-bit-insts}}
15 …gcn_ldexph(a, b); // expected-error {{'__builtin_amdgcn_ldexph' needs target feature 16-bit-insts}}
16 …xp_manth(a); // expected-error {{'__builtin_amdgcn_frexp_manth' needs target feature 16-bit-insts}}
17 …rexp_exph(a); // expected-error {{'__builtin_amdgcn_frexp_exph' needs target feature 16-bit-insts}}
18 …amdgcn_fracth(a); // expected-error {{'__builtin_amdgcn_fracth' needs target feature 16-bit-insts}}
[all …]
/llvm-project-15.0.7/llvm/test/MC/MSP430/
H A Daddrmode.s148 bit r5, r7 ; CHECK: bit r5, r7 ; encoding: [0x07,0xb5]
149 bit 2(r5), r7 ; CHECK: bit 2(r5), r7 ; encoding: [0x17,0xb5,0x02,0x00]
150 bit #-1, r7 ; CHECK: bit #-1, r7 ; encoding: [0x37,0xb3]
151 bit #42, r7 ; CHECK: bit #42, r7 ; encoding: [0x37,0xb0,0x2a,0x00]
152 bit @r5, r7 ; CHECK: bit @r5, r7 ; encoding: [0x27,0xb5]
153 bit @r5+, r7 ; CHECK: bit @r5+, r7 ; encoding: [0x37,0xb5]
155 bit r5, 2(r7) ; CHECK: bit r5, 2(r7) ; encoding: [0x87,0xb5,0x02,0x00]
156 bit 2(r7), 2(r7) ; CHECK: bit 2(r7), 2(r7) ; encoding: [0x97,0xb7,0x02,0x00,0x02,0x00]
157 bit #-1, 2(r7) ; CHECK: bit #-1, 2(r7) ; encoding: [0xb7,0xb3,0x02,0x00]
159 bit @r5, 2(r7) ; CHECK: bit @r5, 2(r7) ; encoding: [0xa7,0xb5,0x02,0x00]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips-dspr2/
H A Dinvalid.s4 balign $2, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
5 balign $2, $3, 4 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
6 shra.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
7 shra.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
8 shra_r.qb $3, $4, 8 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
9 shra_r.qb $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
10 shrl.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
11 shrl.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
12 append $3, $4, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
13 append $3, $4, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dx86-64-bittest-logic.ll50 %a = or i64 %x, 2147483648 ; set bit 31
60 %a = or i64 %x, 4294967296 ; set bit 32
90 %a = xor i64 %x, 2147483648 ; toggle bit 31
100 %a = xor i64 %x, 4294967296 ; toggle bit 32
170 %a = or i64 %x, 2147483648 ; set bit 31
180 %a = or i64 %x, 4294967296 ; set bit 32
210 %a = xor i64 %x, 2147483648 ; toggle bit 31
220 %a = xor i64 %x, 4294967296 ; toggle bit 32
290 %a = or i64 %x, 2147483648 ; set bit 31
300 %a = or i64 %x, 4294967296 ; set bit 32
[all …]
/llvm-project-15.0.7/lldb/include/lldb/Core/
H A DPropertiesBase.td15 bit Global = 1;
20 bit HasDefaultUnsignedValue = 1;
21 bit HasDefaultBooleanValue = 1;
26 bit HasDefaultUnsignedValue = 1;
27 bit HasDefaultBooleanValue = 1;
33 bit HasDefaultStringValue = 1;
39 bit HasDefaultEnumValue = 1;
45 bit HasDefaultUnsignedValue = 1;
56 bit HasElementType = 1;
/llvm-project-15.0.7/compiler-rt/test/cfi/
H A DREADME.txt2 functionality associated with bit sets of different sizes. When certain
3 macros are defined the tests instantiate classes that force the bit sets
6 - B32 forces 32-bit bit sets.
7 - B64 forces 64-bit bit sets.
8 - BM forces memory bit sets.

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