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/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/
H A Dbitfield-bittests.ll29 %bf.cast = zext i8 %bf.clear to i32
31 %bf.clear2 = and i8 %bf.lshr, 1
33 %or = or i32 %bf.cast, %bf.cast3
35 %bf.clear6 = and i8 %bf.lshr5, 1
39 %bf.clear11 = and i8 %bf.lshr10, 1
59 %bf.clear2 = and i8 %bf.lshr, 1
61 %or = or i32 %bf.cast, %bf.cast3
63 %bf.clear6 = and i8 %bf.lshr5, 1
87 %bf.clear2 = and i8 %bf.lshr, 1
91 %bf.clear6 = and i8 %bf.lshr5, 1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dbitfieldinsert.ll26 %bf.shl = shl nuw nsw i64 %1, 5
27 %bf.clear = and i64 %bf.load, -2097121
28 %bf.set = or i64 %bf.clear, %bf.shl
55 %bf.value = shl i32 %v, 8
56 %bf.shl = and i32 %bf.value, 16776960
57 %bf.clear = and i32 %bf.load, -16776961
58 %bf.set = or i32 %bf.clear, %bf.shl
87 %bf.clear = and i32 %bf.load, -1048561
88 %bf.set = or i32 %bf.clear, %bf.shl
116 %bf.clear = and i32 %bf.load, -2097121
[all …]
H A Dppc32-lshrti3.ll16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
19 %bf.cast = and i32 %bf.lshr.tr, 65535
20 %dec = add nsw i32 %bf.lshr.tr, 65535
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
26 %tobool = icmp eq i32 %bf.cast, 0
[all …]
H A Dload-shift-combine.ll22 …%bf.load1 = load i96, i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847], [5…
23 %bf.clear2 = and i96 %bf.load1, 302231454903657293676543
24 %bf.set3 = or i96 %bf.clear2, -38383394772764476296921088
25 …store i96 %bf.set3, i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847], [5 x…
30 …%bf.load15 = load i96, i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847], […
31 %bf.clear16 = and i96 %bf.load15, -18446744069414584321
32 %bf.set17 = or i96 %bf.clear16, 18446743532543672320
33 …store i96 %bf.set17, i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847], [5 …
H A Daddi-offset-fold.ll20 %a.4.a.4.bf.load = load i40, i40* %a.4.a.4..sroa_cast, align 4
21 %bf.lshr = lshr i40 %a.4.a.4.bf.load, 31
22 %bf.lshr.tr = trunc i40 %bf.lshr to i32
23 %bf.cast = and i32 %bf.lshr.tr, 127
24 ret i32 %bf.cast
H A Dreloc-align.ll27 %bf.load = load i64, i64* %0, align 1
28 %bf.shl = shl i64 %bf.load, 26
29 %bf.ashr = ashr i64 %bf.shl, 54
30 %bf.cast = trunc i64 %bf.ashr to i32
31 ret i32 %bf.cast
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Ddins.ll40 %bf.clear = and i64 %bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load, 134217727
41 %bf.set = or i64 %bf.clear, 16508780544
44 %bf.clear3 = and i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load2, -16911433729
45 %bf.set4 = or i64 %bf.clear3, 1073741824
48 %bf.clear7 = and i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load6, 1125899906842623
49 %bf.set8 = or i64 %bf.clear7, 5629499534213120
52 %bf.lshr = lshr i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load11, 50
54 %bf.shl = shl nuw nsw i64 %bf.lshr, 34
56 %bf.set15 = or i64 %bf.clear14, %bf.shl
59 %bf.lshr18 = lshr i64 %bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load17, 27
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dinsert-basic.ll31 %bf.value = and i32 %y1, 8388607
35 %3 = or i32 %2, %bf.value
37 %bf.value1 = and i32 %y2, 131071
39 %4 = bitcast i8* %bf.field.offs to i32*
42 %7 = or i32 %6, %bf.value1
44 %bf.value2 = and i32 %y3, 262143
49 %11 = or i32 %10, %bf.value2
51 %bf.value4 = and i32 %y4, 4194303
56 %15 = or i32 %14, %bf.value4
58 %bf.value6 = and i32 %y5, 4095
[all …]
H A Dbit-extract.ll34 %bf.lshr = lshr i32 %x, 8
35 %bf.clear = and i32 %bf.lshr, 65535
36 ret i32 %bf.clear
70 %bf.shl = shl i32 %x, 8
71 %bf.ashr = ashr i32 %bf.shl, 16
72 ret i32 %bf.ashr
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A D2013-03-05-Combine-BitcastTy-Into-Alloca.ll22 %bf.value = shl nuw nsw i96 %0, 6
23 %bf.clear = and i96 %k.sroa.0.0.copyload, -288230376151711744
25 %bf.value2 = shl nuw nsw i96 %1, 32
26 %bf.shl3 = and i96 %bf.value2, 288230371856744448
27 %bf.value.masked = and i96 %bf.value, 4294967232
29 %bf.value8 = and i96 %2, 63
30 %bf.clear4 = or i96 %bf.shl3, %bf.value.masked
31 %bf.set5 = or i96 %bf.clear4, %bf.value8
32 %bf.set10 = or i96 %bf.set5, %bf.clear
34 store i96 %bf.set10, i96* %retval.0.cast7, align 8
[all …]
H A Dpr35515.ll10 %bf.load81 = load i40, i40* bitcast ({ i8, i8, i8, i8, i8 }* @g_49 to i40*), align 2
11 %bf.clear = and i40 %bf.load81, -274869518337
12 …%bf.set = or i40 %bf.clear, shl (i40 zext (i1 icmp sgt (i32 zext (i1 icmp eq (i8* getelementptr in…
13 %tmp = lshr i40 %bf.set, 23
17 %bf.shl154 = zext i32 %tmp3 to i40
18 %bf.set156 = or i40 %bf.clear, %bf.shl154
19 ret i40 %bf.set156
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dzext-logicop-shift-load.ll23 %bf.clear = shl i8 %bf.load, 2
24 %0 = and i8 %bf.clear, 60
46 %bf.clear = shl i8 %bf.load, 2
47 %0 = and i8 %bf.clear, 60
74 %bf.clear = shl i8 %bf.load, 2
75 %0 = xor i8 %bf.clear, 60
98 %bf.clear = lshr i8 %bf.load, 2
99 %0 = and i8 %bf.clear, 60
122 %bf.clear = lshr i8 %bf.load, 2
146 %bf.clear = lshr i8 %bf.load, 2
[all …]
H A Dclear-bitfield.ll12 %bf.load = load i32, ptr %ptr
13 %bf.clear = and i32 %bf.load, -2
14 store i32 %bf.clear, ptr %ptr
24 %bf.load = load i16, ptr %ptr
25 %bf.clear = and i16 %bf.load, -2
26 store i16 %bf.clear, ptr %ptr
H A Dpr3216.ll12 %bf.lo = lshr i8 %tmp, 5
13 %bf.lo.cleared = and i8 %bf.lo, 7
14 %1 = shl i8 %bf.lo.cleared, 5
15 %bf.val.sext = ashr i8 %1, 5
16 %conv = sext i8 %bf.val.sext to i32
H A Dnarrow_op-1.ll4 %struct.bf = type { i64, i16, i16, i32 }
5 @bfi = common dso_local global %struct.bf zeroinitializer, align 16
13 %0 = load i32, ptr getelementptr (%struct.bf, ptr @bfi, i32 0, i32 1), align 8
15 store i32 %1, ptr getelementptr (%struct.bf, ptr @bfi, i32 0, i32 1), align 8
25 %0 = load i32, ptr getelementptr (%struct.bf, ptr @bfi, i32 0, i32 1), align 1
27 store i32 %1, ptr getelementptr (%struct.bf, ptr @bfi, i32 0, i32 1), align 1
37 %0 = load i32, ptr getelementptr (%struct.bf, ptr @bfi, i32 0, i32 1), align 8
39 store i32 %1, ptr getelementptr (%struct.bf, ptr @bfi, i32 0, i32 1), align 8
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A Dsimp-to-self.ll5 ; CHECK-NEXT: %bf.clear = and i32 %lv, -131072
6 ; CHECK-NEXT: %bf.set = or i32 1, %bf.clear
18 %bf.clear = and i32 %lv, -131072
19 %bf.set = or i32 %conv, %bf.clear
20 %bf.clear.1 = and i32 %bf.set, -131072
21 %bf.set.1 = or i32 1, %bf.clear.1
25 store i32 %bf.set.1, i32* bitcast (i64* @a to i32*)
H A Dpr32836.ll34 %bf.load1 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @b, i64 0, i32 0)
35 %bf.value = and i32 %tmp1, 536870911
36 %bf.clear = and i32 %bf.load1, -536870912
37 %bf.set = or i32 %bf.clear, %bf.value
38 store i32 %bf.set, i32* getelementptr (%struct.anon, %struct.anon* @b, i64 0, i32 0)
41 %bf.load4 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @b, i64 0, i32 0)
42 %tmp4 = and i32 %bf.load4, 536870911
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dpr56110.ll13 %bf.load = load i96, ptr %a, align 1
15 %bf.value = zext i32 %0 to i96
16 %bf.shl = shl nuw nsw i96 %bf.value, 24
17 %bf.clear = and i96 %bf.load, -1099494850561
18 %bf.set = or i96 %bf.clear, %bf.shl
19 store i96 %bf.set, ptr %a, align 1
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
H A Dload_split_because_of_memsize_or_align.ll53 %bf.cast = zext i24 %bf.load to i32
79 %bf.cast = zext i24 %bf.load to i32
103 %bf.cast = zext i24 %bf.load to i32
127 %bf.cast = zext i24 %bf.load to i32
155 %bf.cast = zext i40 %bf.load to i64
183 %bf.cast = zext i40 %bf.load to i64
209 %bf.cast = zext i40 %bf.load to i64
235 %bf.cast = zext i40 %bf.load to i64
265 %bf.cast = zext i48 %bf.load to i64
293 %bf.cast = zext i48 %bf.load to i64
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-profgen/Inputs/
H A Dprofile-density-cs.raw.prof7 875-8bf:1223
9 893-8bf:176
15 8bf->870:2022
50 6b0-6bf:2082
53 6b9-6bf:170
65 6bf->6d0:2307
120 6b0-6bf:1093
123 6b9-6bf:226
136 6bf->6d0:1391
H A Dfs-discriminator.raw.prof12 6b0-6bf:1
15 6b9-6bf:1
43 875-8bf:1
45 893-8bf:1
53 6bf->6d0:1
75 8bf->870:1
/llvm-project-15.0.7/clang/test/CoverageMapping/
H A Dlogical.cpp5 bool bf = false; in main() local
6 bool a = bt && bf; // CHECK-NEXT: File 0, [[@LINE]]:12 -> [[@LINE]]:14 = #0 in main()
12 …bf; // CHECK-NEXT: Branch,File 0, [[@LINE-1]]:7 -> [[@LINE-1]]:9 = #3, (… in main()
15 a = bf || bt; // CHECK-NEXT: File 0, [[@LINE]]:7 -> [[@LINE]]:9 = #0 in main()
20 a = bf || // CHECK-NEXT: File 0, [[@LINE]]:7 -> [[@LINE]]:9 = #0 in main()
/llvm-project-15.0.7/clang/test/Sema/
H A Dformat-strings-bitfield-promotion.c11 } bf; variable
14 …printf("%ld", bf.a); // expected-warning {{format specifies type 'long' but the argument has type … in bitfield_promotion()
15 …printf("%lu", bf.b); // expected-warning {{format specifies type 'unsigned long' but the argument … in bitfield_promotion()
16 …printf("%ld", bf.c); // expected-warning {{format specifies type 'long' but the argument has type … in bitfield_promotion()
17 …printf("%lu", bf.d); // expected-warning {{format specifies type 'unsigned long' but the argument … in bitfield_promotion()
H A Dformat-strings-bitfield-promotion.cxx14 } bf; variable
17 printf("%ld", bf.a); in bitfield_promotion()
18 printf("%lu", bf.b); in bitfield_promotion()
19 printf("%ld", bf.c); in bitfield_promotion()
20 printf("%lu", bf.d); in bitfield_promotion()
/llvm-project-15.0.7/libcxx/test/std/utilities/utility/utility.underlying/
H A Dto_underlying.pass.cpp69 WithBitfieldEnums bf; in test() local
70 bf.e1 = static_cast<e_default>(3); in test()
71 bf.e2 = e_ushort::e; in test()
72 bf.e3 = e_bool::t; in test()
73 assert(3 == std::to_underlying(bf.e1)); in test()
74 assert(25 == std::to_underlying(bf.e2)); in test()
75 assert(1 == std::to_underlying(bf.e3)); in test()

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