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Searched refs:asrl (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/mve-intrinsics/
H A Dlongshift-const.ll4 declare {i32, i32} @llvm.arm.mve.asrl(i32, i32, i32)
15 %3 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %2, i32 %1, i32 0)
28 ; CHECK-NEXT: asrl r0, r1, #23
34 %3 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %2, i32 %1, i32 23)
47 ; CHECK-NEXT: asrl r0, r1, #32
53 %3 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %2, i32 %1, i32 32)
67 ; CHECK-NEXT: asrl r0, r1, r2
87 ; CHECK-NEXT: asrl r0, r1, r2
107 ; CHECK-NEXT: asrl r0, r1, r2
165 ; CHECK-NEXT: asrl r0, r1, r2
[all …]
H A Dlongshift-demand.ll10 ; CHECK-NEXT: asrl r0, r1, #3
91 ; CHECK-NEXT: asrl r0, r1, #31
172 ; CHECK-NEXT: asrl r0, r1, #32
254 ; CHECK-NEXT: asrl r0, r1, r2
296 ; CHECK-NEXT: asrl r0, r1, r2
343 ; CHECK-NEXT: asrl r0, r1, #3
432 ; CHECK-NEXT: asrl r0, r1, #31
521 ; CHECK-NEXT: asrl r0, r1, #32
611 ; CHECK-NEXT: asrl r0, r1, r2
657 ; CHECK-NEXT: asrl r0, r1, r2
[all …]
H A Dscalar-shifts.ll7 ; CHECK-NEXT: asrl r0, r1, r2
13 %3 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %2, i32 %1, i32 %shift)
23 declare { i32, i32 } @llvm.arm.mve.asrl(i32, i32, i32)
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dmve-scalar-shift.s11 # CHECK: asrl r0, r1, #23 @ encoding: [0x50,0xea,0xef,0x51]
13 asrl r0, r1, #23 label
15 # CHECK: asrl lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
17 asrl lr, r1, #27 label
26 asrl r3, r2, #33 label
31 asrl r0, r1, #33 label
35 asrl r0, r0, #32 label
37 # CHECK: asrl r0, r1, r4 @ encoding: [0x50,0xea,0x2d,0x41]
39 asrl r0, r1, r4 label
43 asrl r0, r0, r4 label
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-laneinterleaving-cost.ll35 ; CHECK-NEXT: asrl r2, r1, r4
41 ; CHECK-NEXT: asrl r6, r1, r3
49 ; CHECK-NEXT: asrl r0, r1, r3
55 ; CHECK-NEXT: asrl r6, r1, r2
171 ; CHECK-NEXT: asrl r2, r1, r5
177 ; CHECK-NEXT: asrl r4, r1, r7
185 ; CHECK-NEXT: asrl r0, r1, r7
191 ; CHECK-NEXT: asrl r6, r1, r2
294 ; CHECK-NEXT: asrl r0, r5, r3
299 ; CHECK-NEXT: asrl r4, r5, r3
[all …]
H A Dmve-shifts.ll149 ; CHECK-NEXT: asrl r2, r1, r0
152 ; CHECK-NEXT: asrl r0, r5, r3
289 ; CHECK-NEXT: asrl r0, r1, #4
290 ; CHECK-NEXT: asrl r2, r3, #4
458 ; CHECK-NEXT: asrl r12, r1, r0
459 ; CHECK-NEXT: asrl r2, r3, r0
H A Dmve-pipelineloops.ll108 ; CHECK-NEXT: asrl r4, r7, #6
109 ; CHECK-NEXT: asrl r6, r5, #6
261 %55 = tail call { i32, i32 } @llvm.arm.mve.asrl(i32 %accReal.3.off0, i32 %accReal.3.off32, i32 6)
264 %57 = tail call { i32, i32 } @llvm.arm.mve.asrl(i32 %accImag.3.off0, i32 %accImag.3.off32, i32 6)
274 declare { i32, i32 } @llvm.arm.mve.asrl(i32, i32, i32) #1
H A Dmve-vqshrn.ll188 ; CHECK-NEXT: asrl r0, r1, #3
189 ; CHECK-NEXT: asrl r2, r3, #3
250 ; CHECK-NEXT: asrl r2, r1, #3
253 ; CHECK-NEXT: asrl r4, r5, #3
H A Dmve-laneinterleaving.ll353 ; CHECK-NEXT: asrl r0, r5, r1
360 ; CHECK-NEXT: asrl r4, r5, r2
393 ; CHECK-NEXT: asrl r4, r5, r1
402 ; CHECK-NEXT: asrl r6, r5, r2
H A Dshift_parts.ll157 ; CHECK-MVE-NEXT: asrl r0, r1, r2
182 ; CHECK-MVE-NEXT: asrl r0, r1, #3
H A Dmve-satmul-loops.ll42 ; CHECK-NEXT: asrl r4, r11, #31
49 ; CHECK-NEXT: asrl r6, r3, #31
91 ; CHECK-NEXT: asrl r4, r3, #31
241 ; CHECK-NEXT: asrl r4, r7, #31
248 ; CHECK-NEXT: asrl r10, r5, #31
276 ; CHECK-NEXT: asrl r4, r7, #31
283 ; CHECK-NEXT: asrl r6, r3, #31
325 ; CHECK-NEXT: asrl r4, r1, #31
480 ; CHECK-NEXT: asrl r10, r5, #31
486 ; CHECK-NEXT: asrl r6, r7, #31
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dmve-scalar-shift.txt6 # CHECK: asrl r0, r1, #23 @ encoding: [0x50,0xea,0xef,0x51]
10 # CHECK: asrl lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
14 # CHECK: asrl r0, r1, r4 @ encoding: [0x50,0xea,0x2d,0x41]
/llvm-project-15.0.7/llvm/test/CodeGen/M68k/ShiftRotate/
H A Dasr.ll32 define i32 @asrl(i32 %a, i32 %b) nounwind {
33 ; CHECK-LABEL: asrl:
/llvm-project-15.0.7/clang/test/CodeGen/arm-mve-intrinsics/
H A Dscalar-shifts.c24 return asrl(value, shift); in test_asrl()
/llvm-project-15.0.7/clang/test/Driver/
H A Darmv8.1m.main.s61 asrl r0, r1, r2 label
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dwhile-loops.ll204 ; CHECK-NEXT: asrl r0, r1, r2
218 ; CHECK-NEXT: asrl r6, r5, r0
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_mve.td1271 def asrl: LongScalarShift<s64, (args s32:$sh), (IRInt<"asrl"> $lo, $hi, $sh)>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrMVE.td568 def MVE_ASRLr : MVE_ScalarShiftDRegReg<"asrl", 0b1, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
571 def MVE_ASRLi : MVE_ScalarShiftDRegImm<"asrl", 0b10, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,