| /llvm-project-15.0.7/llvm/utils/gn/secondary/compiler-rt/lib/builtins/ |
| H A D | BUILD.gn | 387 "arm/clzdi2.S",
388 "arm/clzsi2.S",
391 "arm/divsi3.S",
392 "arm/fp_mode.c",
393 "arm/modsi3.S",
396 "arm/switch8.S",
470 "arm/chkstk.S",
579 "arm/addsf3.S",
580 "arm/comparesf2.S",
581 "arm/divsi3.S",
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | intrinsics-coprocessor.ll | 22 tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind
44 declare void @llvm.arm.ldc(i32, i32, i8*) nounwind
46 declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind
48 declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
50 declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
52 declare void @llvm.arm.stc(i32, i32, i8*) nounwind
54 declare void @llvm.arm.stcl(i32, i32, i8*) nounwind
56 declare void @llvm.arm.stc2(i32, i32, i8*) nounwind
58 declare void @llvm.arm.stc2l(i32, i32, i8*) nounwind
74 declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind
[all …]
|
| H A D | acle-intrinsics.ll | 13 %tmp = call i32 @llvm.arm.ssat(i32 %a, i32 32)
21 %tmp = call i32 @llvm.arm.ssat(i32 %a, i32 1)
29 %tmp = call i32 @llvm.arm.usat(i32 %a, i32 31)
37 %tmp = call i32 @llvm.arm.usat(i32 %a, i32 0)
66 %tmp1 = call i32 @llvm.arm.sxtb16(i32 %tmp)
68 %tmp3 = call i32 @llvm.arm.uxtb16(i32 %tmp2)
75 %tmp = call i32 @llvm.arm.sel(i32 %a, i32 %b)
427 declare i32 @llvm.arm.sxtab16(i32, i32)
428 declare i32 @llvm.arm.sxtb16(i32)
429 declare i32 @llvm.arm.uxtab16(i32, i32)
[all …]
|
| H A D | misched-fusion-aes.ll | 3 declare <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d, <16 x i8> %k)
4 declare <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %d)
5 declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d, <16 x i8> %k)
6 declare <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %d)
18 %f00 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e00)
20 %f01 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e01)
22 %f02 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e02)
24 %f03 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e03)
28 %f10 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e00)
30 %f11 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e01)
[all …]
|
| H A D | acle-intrinsics-v5.ll | 11 %tmp = call i32 @llvm.arm.smulbb(i32 %a, i32 %b)
18 %tmp = call i32 @llvm.arm.smulbt(i32 %a, i32 %b)
25 %tmp = call i32 @llvm.arm.smultb(i32 %a, i32 %b)
32 %tmp = call i32 @llvm.arm.smultt(i32 %a, i32 %b)
39 %tmp = call i32 @llvm.arm.smulwb(i32 %a, i32 %b)
70 %tmp = call i32 @llvm.arm.qadd(i32 %a, i32 %b)
77 %tmp = call i32 @llvm.arm.qsub(i32 %a, i32 %b)
84 %dbl = call i32 @llvm.arm.qadd(i32 %a, i32 %a)
92 %dbl = call i32 @llvm.arm.qadd(i32 %b, i32 %b)
109 declare i32 @llvm.arm.qadd(i32, i32) nounwind
[all …]
|
| H A D | intrinsics-crypto.ll | 10 %tmp5 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %tmp4)
12 %tmp6 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %tmp5)
22 %resscalar = call i32 @llvm.arm.neon.sha1h(i32 %scalar)
46 declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8>, <16 x i8>)
47 declare <16 x i8> @llvm.arm.neon.aese(<16 x i8>, <16 x i8>)
48 declare <16 x i8> @llvm.arm.neon.aesimc(<16 x i8>)
49 declare <16 x i8> @llvm.arm.neon.aesmc(<16 x i8>)
50 declare i32 @llvm.arm.neon.sha1h(i32)
51 declare <4 x i32> @llvm.arm.neon.sha1c(<4 x i32>, i32, <4 x i32>)
58 declare <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32>, <4 x i32>)
[all …]
|
| H A D | frame-chain-reserved-fp.ll | 1 ; RUN: not llc -mtriple arm-arm-none-eabi -filetype asm -o - %s -frame-pointer=all 2>&1 | FileCheck…
2 ; RUN: not llc -mtriple arm-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-fr…
3 ; RUN: not llc -mtriple arm-arm-none-eabi -filetype asm -o - %s -frame-pointer=all -mattr=+aapcs-fr…
4 ; RUN: llc -mtriple arm-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf 2>&1 | FileChec…
5 ; RUN: not llc -mtriple arm-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aap…
6 ; RUN: not llc -mtriple arm-arm-none-eabi -filetype asm -o - %s -frame-pointer=non-leaf -mattr=+aap…
7 ; RUN: llc -mtriple arm-arm-none-eabi -filetype asm -o - %s -frame-pointer=none 2>&1 | FileCheck %s…
8 ; RUN: not llc -mtriple arm-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-f…
9 ; RUN: not llc -mtriple arm-arm-none-eabi -filetype asm -o - %s -frame-pointer=none -mattr=+aapcs-f…
|
| H A D | vcvt-v8.ll | 6 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %tmp1)
14 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %tmp1)
22 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %tmp1)
30 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %tmp1)
38 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %tmp1)
46 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %tmp1)
54 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %tmp1)
62 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float> %tmp1)
70 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %tmp1)
78 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %tmp1)
[all …]
|
| H A D | arm-eabi.ll | 1 ; RUN: llc < %s -mtriple=arm-none-eabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EA…
2 ; RUN: llc < %s -mtriple=arm-none-eabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-…
3 ; RUN: llc < %s -mtriple=arm-none-androideabi -disable-post-ra -o - | FileCheck %s --check-prefix=C…
4 ; RUN: llc < %s -mtriple=arm-none-gnueabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK…
5 ; RUN: llc < %s -mtriple=arm-none-gnueabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHE…
6 ; RUN: llc < %s -mtriple=arm-none-musleabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHEC…
7 ; RUN: llc < %s -mtriple=arm-none-musleabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CH…
8 ; RUN: llc < %s -mtriple=arm-none-eabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-pref…
15 ; RUN: llc < %s -mtriple=arm-none-eabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix…
16 ; RUN: llc < %s -mtriple=arm-none-eabihf -meabi=4 -disable-post-ra -o - | FileCheck %s --check-pref…
[all …]
|
| H A D | ldstrex.ll | 12 %ldrexd = tail call %0 @llvm.arm.ldrexd(i8* %p)
33 declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly
34 declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
63 declare i32 @llvm.arm.ldrex.p0i8(i8*) nounwind readonly
64 declare i32 @llvm.arm.ldrex.p0i16(i16*) nounwind readonly
65 declare i32 @llvm.arm.ldrex.p0i32(i32*) nounwind readonly
92 declare i32 @llvm.arm.strex.p0i8(i32, i8*) nounwind
93 declare i32 @llvm.arm.strex.p0i16(i32, i16*) nounwind
94 declare i32 @llvm.arm.strex.p0i32(i32, i32*) nounwind
99 call void @llvm.arm.clrex()
[all …]
|
| H A D | vrec.ll | 1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
7 %tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
15 %tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
23 %tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
31 %tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
35 declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone
36 declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
66 %tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
74 %tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
82 %tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
[all …]
|
| H A D | neon-vqaddsub-upgrade.ll | 1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
8 %tmp3 = call <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
17 %tmp3 = call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
26 %tmp3 = call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
35 %tmp3 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
44 %tmp3 = call <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
53 %tmp3 = call <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
62 %tmp3 = call <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
71 %tmp3 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
153 %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
[all …]
|
| H A D | arm-vlddup.ll | 32 declare %struct.uint8x8x2_t @llvm.arm.neon.vld2dup.v8i8.p0i8(i8*, i32)
33 declare %struct.uint16x4x2_t @llvm.arm.neon.vld2dup.v4i16.p0i8(i8*, i32)
34 declare %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0i8(i8*, i32)
35 declare %struct.uint64x1x2_t @llvm.arm.neon.vld2dup.v1i64.p0i8(i8*, i32)
37 declare %struct.uint8x8x3_t @llvm.arm.neon.vld3dup.v8i8.p0i8(i8*, i32)
38 declare %struct.uint16x4x3_t @llvm.arm.neon.vld3dup.v4i16.p0i8(i8*, i32)
39 declare %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0i8(i8*, i32)
40 declare %struct.uint64x1x3_t @llvm.arm.neon.vld3dup.v1i64.p0i8(i8*, i32)
42 declare %struct.uint8x8x4_t @llvm.arm.neon.vld4dup.v8i8.p0i8(i8*, i32)
43 declare %struct.uint16x4x4_t @llvm.arm.neon.vld4dup.v4i16.p0i8(i8*, i32)
[all …]
|
| H A D | vhadd.ll | 1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
8 %tmp3 = call <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
17 %tmp3 = call <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
26 %tmp3 = call <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
35 %tmp3 = call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
44 %tmp3 = call <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
53 %tmp3 = call <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
111 declare <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
115 declare <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
132 %tmp3 = call <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
[all …]
|
| H A D | vld-vst-upgrade.ll | 1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon < %s | FileCheck %s
2 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -opaque-pointers < %s | FileCheck %s
13 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %ptr, i32 1)
17 declare <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) nounwind readonly
22 %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8* %ptr, i32 1)
31 %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %ptr, i32 1)
40 %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %ptr, i32 1)
80 call void @llvm.arm.neon.vst1.v2i32(i8* %ptr, <2 x i32> %A, i32 1)
84 declare void @llvm.arm.neon.vst1.v2i32(i8*, <2 x i32>, i32) nounwind
89 call void @llvm.arm.neon.vst2.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, i32 1)
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/ |
| H A D | intrinsics-coprocessor.ll | 21 tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind
29 tail call void @llvm.arm.stc(i32 7, i32 3, i8* %i) nounwind
59 declare void @llvm.arm.ldc(i32, i32, i8*) nounwind
61 declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind
63 declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
65 declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
67 declare void @llvm.arm.stc(i32, i32, i8*) nounwind
69 declare void @llvm.arm.stcl(i32, i32, i8*) nounwind
71 declare void @llvm.arm.stc2(i32, i32, i8*) nounwind
73 declare void @llvm.arm.stc2l(i32, i32, i8*) nounwind
[all …]
|
| H A D | mve-pred-constfold.ll | 20 %0 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 13107)
22 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 52428)
53 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
57 %5 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
149 %4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1)
370 declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)
371 declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>)
372 declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>)
374 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
375 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
[all …]
|
| /llvm-project-15.0.7/compiler-rt/lib/builtins/ |
| H A D | CMakeLists.txt | 377 arm/fp_mode.c
380 arm/clzdi2.S
381 arm/clzsi2.S
384 arm/divsi3.S
385 arm/modsi3.S
407 arm/udivsi3.S
408 arm/umodsi3.S
413 arm/divsi3.S
414 arm/udivsi3.S
416 arm/addsf3.S
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/mve-intrinsics/ |
| H A D | v2i1-upgrade.ll | 4 declare <4 x i1> @llvm.arm.mve.vctp64(i32)
5 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
6 declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)
35 %0 = call <4 x i1> @llvm.arm.mve.vctp64(i32 %a)
36 %1 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %0)
56 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
57 %2 = call <4 x i1> @llvm.arm.mve.vctp64(i32 %a)
59 %4 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %3)
93 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
110 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
[all …]
|
| H A D | absneg-predicated.ll | 14 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
28 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
42 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
56 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
70 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
84 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
98 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
112 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
313 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
314 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
[all …]
|
| H A D | vrint-predicated.ll | 13 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
27 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
41 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
55 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
69 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
83 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
97 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
111 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
125 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
172 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
[all …]
|
| /llvm-project-15.0.7/llvm/test/Analysis/BasicAA/ |
| H A D | cs-cs-arm.ll | 2 ; REQUIRES: arm
5 target triple = "arm-apple-ios"
7 declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8*, i32) nounwind readonly
8 declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind
13 %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) nounwind
14 call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %q, <8 x i16> %y, i32 16)
28 …oModRef: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) #{{[0-9]+}} <-> ca…
29 …ef: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) #{{[0-9]+}} <-> %b = ca…
30 …K: NoModRef: call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %q, <8 x i16> %y, i32 16) <-> %a = c…
31 …K: NoModRef: call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %q, <8 x i16> %y, i32 16) <-> %b = c…
[all …]
|
| /llvm-project-15.0.7/llvm/test/Verifier/ARM/ |
| H A D | intrinsic-immarg.ll | 3 declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
16 declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
28 declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind
33 %ret0 = call { i32, i32 } @llvm.arm.mrrc(i32 %arg0, i32 0, i32 0)
47 declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind
66 declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind
71 call void @llvm.arm.mcrr(i32 %arg0, i32 1, i32 2, i32 3, i32 4)
85 declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind
104 declare i32 @llvm.arm.space(i32, i32) nounwind
108 ; CHECK-NEXT: call i32 @llvm.arm.space(i32 %arg0, i32 %arg1)
[all …]
|
| /llvm-project-15.0.7/llvm/test/Bitcode/ |
| H A D | arm-intrinsics.ll | 1 ; RUN: llvm-dis < %S/arm-intrinsics.bc | FileCheck %s
4 ; CHECK: call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32)
5 %a = call i32 @llvm.arm.ldrex.p0i32(i32* %p)
7 %c = call i32 @llvm.arm.strex.p0i32(i32 0, i32* %p)
9 ; CHECK: call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32)
10 %a2 = call i32 @llvm.arm.ldaex.p0i32(i32* %p)
12 %c2 = call i32 @llvm.arm.stlex.p0i32(i32 0, i32* %p)
16 declare i32 @llvm.arm.ldrex.p0i32(i32*)
17 declare i32 @llvm.arm.ldaex.p0i32(i32*)
18 declare i32 @llvm.arm.stlex.p0i32(i32, i32*)
[all …]
|
| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/ARM/ |
| H A D | mve-v2i2v.ll | 2 ; RUN: opt -passes=instcombine -S -mtriple=arm -o - %s | FileCheck %s
6 declare i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1>)
7 declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)
8 declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>)
9 declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>)
11 declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32)
12 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
13 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
14 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
25 %int = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %vin)
[all …]
|