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/llvm-project-15.0.7/flang/test/Lower/OpenMP/
H A Domp-parallel-firstprivate-clause-scalar.f9059 integer(kind=8) :: arg5 local
63 call bar(arg1, arg2, arg3, arg4, arg5, arg6)
95 logical(kind=8) :: arg5 local
98 call baz(arg1, arg2, arg3, arg4, arg5)
133 real(kind=10) :: arg5 local
137 call qux(arg1, arg2, arg3, arg4, arg5, arg6)
/llvm-project-15.0.7/mlir/test/Conversion/SCFToOpenMP/
H A Dscf-to-openmp.mlir5 %arg3: index, %arg4: index, %arg5: index) {
7 …for (%[[LVAR1:.*]], %[[LVAR2:.*]]) : index = (%arg0, %arg1) to (%arg2, %arg3) step (%arg4, %arg5) {
9 scf.parallel (%i, %j) = (%arg0, %arg1) to (%arg2, %arg3) step (%arg4, %arg5) {
22 %arg3: index, %arg4: index, %arg5: index) {
28 // CHECK: omp.wsloop for (%[[LVAR_IN1:.*]]) : index = (%arg1) to (%arg3) step (%arg5) {
30 scf.parallel (%j) = (%arg1) to (%arg3) step (%arg5) {
45 %arg3: index, %arg4: index, %arg5: index) {
59 // CHECK: omp.wsloop for (%[[LVAR_AL2:.*]]) : index = (%arg1) to (%arg3) step (%arg5) {
61 scf.parallel (%j) = (%arg1) to (%arg3) step (%arg5) {
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dconv-interface-invalid.mlir40 ^bb0(%arg3 : f32, %arg4 : f32, %arg5 : f32):
41 linalg.yield %arg5 : f32
58 ^bb0(%arg3 : f32, %arg4 : f32, %arg5 : f32):
59 linalg.yield %arg5 : f32
77 linalg.yield %arg5 : f32
95 linalg.yield %arg5 : f32
115 linalg.yield %arg5 : f32
134 linalg.yield %arg5 : f32
153 linalg.yield %arg5 : f32
172 linalg.yield %arg5 : f32
[all …]
H A Dfusion.mlir20 scf.for %arg5 = %c0 to %0 step %c2 {
68 scf.for %arg5 = %c0 to %0 step %c2 {
120 scf.for %arg5 = %c0 to %0 step %c2 {
177 scf.for %arg5 = %c0 to %0 step %c2 {
235 scf.for %arg5 = %c0 to %1 step %c2 {
313 scf.for %arg5 = %c0 to %1 step %c2 {
316 %3 = affine.apply #map0(%arg5)
370 scf.for %arg5 = %c0 to %0 step %c2 {
388 scf.for %arg5 = %c0 to %3 step %c2 {
508 %2 = arith.addf %E, %arg5 : f32
[all …]
H A Dtransform-op-vectorize.mlir47 %arg5: index) -> tensor<24x25xf32> {
50 %0 = affine.min #map0()[%arg5]
51 …%1 = tensor.extract_slice %arg0[%arg3, %arg5] [4, %0] [1, 1] : tensor<24x12xf32> to tensor<4x?xf32>
52 …%2 = tensor.extract_slice %arg1[%arg5, %arg4] [%0, 5] [1, 1] : tensor<12x25xf32> to tensor<?x5xf32>
98 %arg5: index) -> tensor<24x25xf32> {
101 %0 = affine.min #map0()[%arg5]
104 …%1 = tensor.extract_slice %arg0[%arg3, %arg5] [4, %0] [1, 1] : tensor<24x12xf32> to tensor<4x?xf32>
105 …%2 = tensor.extract_slice %arg1[%arg5, %arg4] [%0, 5] [1, 1] : tensor<12x25xf32> to tensor<?x5xf32>
H A Ddetensorize_0d.mlir10 ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
29 ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
38 ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
47 ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
69 ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
90 ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
/llvm-project-15.0.7/mlir/test/Dialect/Affine/
H A Dloop-permute.mlir26 // CHECK-120-NEXT: "foo"(%arg4, %arg5)
35 // CHECK-102-NEXT: "bar"(%arg5)
38 // CHECK-012-NEXT: "bar"(%arg5)
40 // CHECK-021: "foo"(%arg3, %arg5)
43 // CHECK-210: "foo"(%arg5, %arg4)
46 // CHECK-201: "foo"(%arg5, %arg3)
/llvm-project-15.0.7/mlir/test/Analysis/
H A Dtest-liveness.mlir298 %arg3 : i32, %arg4 : i32, %arg5 : i32,
324 // CHECK-NEXT: arg5@0 arg6@0 val_7 val_8
329 %1 = arith.addi %arg4, %arg5 : i32
332 // CHECK-NEXT: LiveIn: arg5@0 arg6@0 val_7
342 %2 = arith.addi %0, %arg5 : i32
385 %arg3 : i32, %arg4 : i32, %arg5 : i32,
388 %1 = arith.addi %arg4, %arg5 : i32
406 %2 = arith.addi %0, %arg5 : i32
452 %arg3 : i32, %arg4 : i32, %arg5 : i32,
455 %1 = arith.addi %arg4, %arg5 : i32
[all …]
H A Dtest-topoligical-sort.mlir11 %arg4 : i32, %arg5 : i32, %arg6 : i32,
13 %0 = arith.addi %arg4, %arg5 {__test_sort_original_idx__ = 0} : i32
16 %2 = arith.addi %0, %arg5 : i32
/llvm-project-15.0.7/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/
H A Dkernel-args.ll8 ; CHECK: DIVERGENT: float %arg5
11 … float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
21 ; CHECK-NOT: %arg5
23 … float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
35 … float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
/llvm-project-15.0.7/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/
H A Dkernel-args.ll8 ; CHECK: DIVERGENT: float %arg5
11 … float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
21 ; CHECK-NOT: %arg5
23 … float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
35 … float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Damdgpu-abi-struct-coerce.cl476 …3 x i32> noundef %arg3, <3 x i32> noundef %arg4, i32 %arg5.coerce0, float %arg5.coerce1, i32 %arg5…
477 void v3i32_reg_count(int3 arg1, int3 arg2, int3 arg3, int3 arg4, struct_arg_t arg5) { }
482 …ir_reg_count(int3_pair *arg0, int3_pair arg1, int3 arg2, int3_pair arg3, int3 arg4, float arg5) { }
487 short4 arg4, short4 arg5, struct_4regs arg6) { }
491 short4 arg4, short4 arg5, short4 arg6, struct_4regs arg7) { }
495 short3 arg4, short3 arg5, struct_4regs arg6) { }
499 short3 arg4, short3 arg5, short3 arg6, struct_4regs arg7) { }
503 short2 arg4, short2 arg5, short2 arg6, short2 arg7,
509 short2 arg4, short2 arg5, short2 arg6, short2 arg7,
515 char2 arg4, char2 arg5, struct_4regs arg6) { }
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/ScalarEvolution/
H A Dsext-mul.ll51 …825300114114700748351602688 + (633825300114114700748351602688 * (zext i32 %arg5 to i127))) to i128)
53 …25300114114700748351602688 + (633825300114114700748351602688 * (zext i32 %arg5 to i127))) to i128)…
54 ; CHECK: Loop %bb7: backedge-taken count is (-1 + (zext i32 %arg5 to i128))<nsw>
56 ; CHECK-NEXT: Loop %bb7: Predicated backedge-taken count is (-1 + (zext i32 %arg5 to i128))<nsw>
58 define void @goo(i32* nocapture %arg3, i32 %arg4, i32 %arg5) {
60 %t = icmp sgt i32 %arg5, 0
64 %t4 = zext i32 %arg5 to i128
/llvm-project-15.0.7/mlir/test/Dialect/MemRef/
H A Dfold-subview-ops.mlir23 %0 = memref.subview %arg0[%arg1, %arg2][4, 4][%arg5, %arg6] :
46 memref.store %arg5, %0[%arg3, %arg4] : memref<4x4xf32, offset:?, strides: [64, 3]>
64 %0 = memref.subview %arg0[%arg1, %arg2][4, 4][%arg5, %arg6] :
106 %0 = memref.subview %arg0[%arg1, %arg2][4, 4][%arg5, %arg6] :
128 %arg3 : index, %arg4 : index, %arg5 : index, %arg6 : index,
168 %arg1: index, %arg2 : index, %arg3 : index, %arg4: index, %arg5 : index,
174 %1 = vector.transfer_read %0[%arg5, %arg6], %cst {in_bounds = [true]}
198 %arg5: index, %arg6 : index, %arg7 : index) {
200 %0 = memref.subview %arg0[0, %arg2, %arg3] [1, %arg4, %arg5] [1, 1, 1]
228 %arg5: index, %arg6 : index, %arg7 : index) {
[all …]
/llvm-project-15.0.7/mlir/test/Target/LLVMIR/
H A Darm-sve.mlir81 %arg5: vector<[4]xi1>)
84 %0 = "arm_sve.intr.add"(%arg5, %arg0, %arg1) : (vector<[4]xi1>,
89 %1 = "arm_sve.intr.sub"(%arg5, %0, %arg1) : (vector<[4]xi1>,
94 %2 = "arm_sve.intr.mul"(%arg5, %1, %arg3) : (vector<[4]xi1>,
99 %3 = "arm_sve.intr.sdiv"(%arg5, %2, %arg4) : (vector<[4]xi1>,
104 %4 = "arm_sve.intr.udiv"(%arg5, %3, %arg4) : (vector<[4]xi1>,
117 %arg5: vector<[4]xi1>)
125 %1 = "arm_sve.intr.fsub"(%arg5, %0, %arg2) : (vector<[4]xi1>,
130 %2 = "arm_sve.intr.fmul"(%arg5, %1, %arg3) : (vector<[4]xi1>,
135 %3 = "arm_sve.intr.fdiv"(%arg5, %2, %arg4) : (vector<[4]xi1>,
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dps-shader-arg-count.ll6 …arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6,…
16 …arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6,…
20 %i3 = extractelement <2 x float> %arg5, i32 1
30 …arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6,…
33 %i3 = extractelement <2 x float> %arg5, i32 1
47 %i3 = extractelement <2 x float> %arg5, i32 1
60 %i3 = extractelement <2 x float> %arg5, i32 1
106 %i3 = extractelement <2 x float> %arg5, i32 1
152 %i3 = extractelement <2 x float> %arg5, i32 1
284 %i3 = extractelement <2 x float> %arg5, i32 1
[all …]
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Affine/
H A DPasses.td113 affine.for %arg5 = 0 to 3 {
115 %0 = affine.load %arg0[%arg5, %arg6] : memref<10x10xf32>
116 %1 = affine.load %arg1[%arg5, %arg6] : memref<10x10xf32>
118 affine.store %2, %arg3[%arg5, %arg6] : memref<10x10xf32>
121 affine.for %arg5 = 0 to 3 {
123 %0 = affine.load %arg0[%arg5, %arg6] : memref<10x10xf32>
124 %1 = affine.load %arg2[%arg5, %arg6] : memref<10x10xf32>
126 affine.store %2, %arg4[%arg5, %arg6] : memref<10x10xf32>
137 affine.for %arg5 = 0 to 3 {
139 %0 = affine.load %arg0[%arg5, %arg6] : memref<10x10xf32>
[all …]
/llvm-project-15.0.7/libc/src/__support/OSUtil/linux/aarch64/
H A Dsyscall.h29 register long x4 __asm__("x4") = arg5;
81 syscall(long number, long arg1, long arg2, long arg3, long arg4, long arg5) { in syscall() argument
89 long arg4, long arg5, in syscall() argument
/llvm-project-15.0.7/flang/test/Semantics/
H A Dresolve72.f9010 subroutine inner1(arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8)
18 type(*), intent(out) :: arg5 local
H A Dresolve71.f9018 subroutine inner(arg1, arg2, arg3, arg4, arg5)
22 class (parenttype), allocatable :: arg5 local
H A Dresolve81.f9048 subroutine testTypeDecl(arg1, arg2, arg3, arg4, arg5, arg6) argument
58 integer, value, intent(in), value :: arg5
/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_win_dll_thunk.h165 void *arg5) { \
168 return fn(arg1, arg2, arg3, arg4, arg5); \
174 void *arg5, void *arg6) { \
177 return fn(arg1, arg2, arg3, arg4, arg5, arg6); \
H A Dsanitizer_syscall_linux_x86_64.inc58 T5 arg5) {
63 "S"((u64)arg2), "d"((u64)arg3), "r"((u64)arg4), "r"((u64)arg5) :
71 T5 arg5, T6 arg6) {
77 "S"((u64)arg2), "d"((u64)arg3), "r"((u64)arg4), "r"((u64)arg5),
/llvm-project-15.0.7/mlir/test/Dialect/Tosa/
H A Dinlining.mlir38 ^bb0(%arg4: tensor<i32>, %arg5: tensor<i32>, %arg6: tensor<i32>, %arg7: tensor<10xi32>):
39 …%2 = call @while_cond_40(%arg4, %arg5, %arg6, %arg7) : (tensor<i32>, tensor<i32>, tensor<i32>, ten…
42 ^bb0(%arg4: tensor<i32>, %arg5: tensor<i32>, %arg6: tensor<i32>, %arg7: tensor<10xi32>):
43 …%2:4 = call @while_body_50(%arg4, %arg5, %arg6, %arg7) : (tensor<i32>, tensor<i32>, tensor<i32>, t…
/llvm-project-15.0.7/mlir/test/mlir-vulkan-runner/
H A Daddf.mlir33 %arg5 = memref.cast %arg2 : memref<8xf32> to memref<?xf32>
36 call @fillResource1DFloat(%arg5, %value0) : (memref<?xf32>, f32) -> ()
43 %arg6 = memref.cast %arg5 : memref<?xf32> to memref<*xf32>

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