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/llvm-project-15.0.7/flang/test/Lower/OpenMP/
H A Domp-parallel-firstprivate-clause-scalar.f9058 integer(kind=4) :: arg4 local
63 call bar(arg1, arg2, arg3, arg4, arg5, arg6)
94 logical(kind=4) :: arg4 local
98 call baz(arg1, arg2, arg3, arg4, arg5)
132 real(kind=8) :: arg4 local
137 call qux(arg1, arg2, arg3, arg4, arg5, arg6)
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Ddetensorize_0d.mlir10 ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
11 %2 = arith.addf %arg3, %arg4 : f32
29 ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
30 %2 = arith.addf %arg3, %arg4 : f32
38 ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
39 %5 = arith.mulf %arg3, %arg4 : f32
47 ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
48 %5 = arith.divf %arg3, %arg4 : f32
69 ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
70 %2 = arith.addf %arg3, %arg4 : f32
[all …]
H A Dtransform-op-vectorize.mlir46 %arg2: tensor<24x25xf32>, %arg3: index, %arg4: index,
52 …%2 = tensor.extract_slice %arg1[%arg5, %arg4] [%0, 5] [1, 1] : tensor<12x25xf32> to tensor<?x5xf32>
53 %3 = tensor.extract_slice %arg2[%arg3, %arg4] [4, 5] [1, 1] : tensor<24x25xf32> to tensor<4x5xf32>
72 …%9 = tensor.insert_slice %8 into %arg2[%arg3, %arg4] [4, 5] [1, 1] : tensor<4x5xf32> into tensor<2…
97 %arg2: tensor<24x25xf32>, %arg3: index, %arg4: index,
105 …%2 = tensor.extract_slice %arg1[%arg5, %arg4] [%0, 5] [1, 1] : tensor<12x25xf32> to tensor<?x5xf32>
106 %3 = tensor.extract_slice %arg2[%arg3, %arg4] [4, 5] [1, 1] : tensor<24x25xf32> to tensor<4x5xf32>
123 …%9 = tensor.insert_slice %8 into %arg2[%arg3, %arg4] [4, 5] [1, 1] : tensor<4x5xf32> into tensor<2…
H A Dconv-interface-invalid.mlir40 ^bb0(%arg3 : f32, %arg4 : f32, %arg5 : f32):
58 ^bb0(%arg3 : f32, %arg4 : f32, %arg5 : f32):
76 ^bb0(%arg3 : f32, %arg4 : f32, %arg5 : f32):
94 ^bb0(%arg3 : f32, %arg4 : f32, %arg5 : f32):
114 ^bb0(%arg3 : f32, %arg4 : f32, %arg5 : f32):
133 ^bb0(%arg3 : f32, %arg4 : f32, %arg5 : f32):
152 ^bb0(%arg3 : f32, %arg4 : f32, %arg5 : f32):
171 ^bb0(%arg3 : f32, %arg4 : f32, %arg5 : f32):
190 ^bb0(%arg3 : f32, %arg4 : f32, %arg5 : f32):
H A Dpad_fusion.mlir4 %arg3 : index, %arg4 : index, %arg5 : f32) -> tensor<?x?xf32> {
18 %1 = tensor.pad %0 low [%arg1, %arg2] high [%arg3, %arg4] {
63 ^bb0(%arg4 : f32, %arg5 : f32):
64 %1 = arith.mulf %arg4, %arg4 : f32
68 ^bb0(%arg4: index, %arg5 : index):
/llvm-project-15.0.7/mlir/test/Conversion/SCFToOpenMP/
H A Dscf-to-openmp.mlir5 %arg3: index, %arg4: index, %arg5: index) {
7 …for (%[[LVAR1:.*]], %[[LVAR2:.*]]) : index = (%arg0, %arg1) to (%arg2, %arg3) step (%arg4, %arg5) {
9 scf.parallel (%i, %j) = (%arg0, %arg1) to (%arg2, %arg3) step (%arg4, %arg5) {
22 %arg3: index, %arg4: index, %arg5: index) {
24 // CHECK: omp.wsloop for (%[[LVAR_OUT1:.*]]) : index = (%arg0) to (%arg2) step (%arg4) {
26 scf.parallel (%i) = (%arg0) to (%arg2) step (%arg4) {
45 %arg3: index, %arg4: index, %arg5: index) {
47 // CHECK: omp.wsloop for (%[[LVAR_AL1:.*]]) : index = (%arg0) to (%arg2) step (%arg4) {
49 scf.parallel (%i) = (%arg0) to (%arg2) step (%arg4) {
H A Dreductions.mlir21 %arg3 : index, %arg4 : index) {
33 step (%arg4, %step) init (%zero) -> (f32) {
67 %arg3 : index, %arg4 : index) {
71 step (%arg4, %step) init (%zero) -> (f32) {
101 %arg3 : index, %arg4 : index) {
105 step (%arg4, %step) init (%zero) -> (f32) {
152 %arg3 : index, %arg4 : index) -> (f32, i64) {
169 step (%arg4, %step) init (%zero, %ione) -> (f32, i64) {
/llvm-project-15.0.7/mlir/test/Dialect/Affine/
H A Dloop-permute.mlir26 // CHECK-120-NEXT: "foo"(%arg4, %arg5)
34 // CHECK-102: "foo"(%arg4, %arg3)
37 // CHECK-012: "foo"(%arg3, %arg4)
41 // CHECK-021-NEXT: "bar"(%arg4)
43 // CHECK-210: "foo"(%arg5, %arg4)
47 // CHECK-201-NEXT: "bar"(%arg4)
/llvm-project-15.0.7/mlir/test/Dialect/Tosa/
H A Dinlining.mlir12 ^bb0(%arg3: tensor<f32>, %arg4: tensor<f32>):
13 %1 = call @add(%arg3, %arg4) : (tensor<f32>, tensor<f32>) -> tensor<f32>
16 ^bb0(%arg3: tensor<f32>, %arg4: tensor<f32>):
17 %1 = call @sub(%arg3, %arg4) : (tensor<f32>, tensor<f32>) -> tensor<f32>
38 ^bb0(%arg4: tensor<i32>, %arg5: tensor<i32>, %arg6: tensor<i32>, %arg7: tensor<10xi32>):
39 …%2 = call @while_cond_40(%arg4, %arg5, %arg6, %arg7) : (tensor<i32>, tensor<i32>, tensor<i32>, ten…
42 ^bb0(%arg4: tensor<i32>, %arg5: tensor<i32>, %arg6: tensor<i32>, %arg7: tensor<10xi32>):
43 …%2:4 = call @while_body_50(%arg4, %arg5, %arg6, %arg7) : (tensor<i32>, tensor<i32>, tensor<i32>, t…
/llvm-project-15.0.7/mlir/test/Dialect/MemRef/
H A Dfold-subview-ops.mlir5 %1 = memref.load %0[%arg3, %arg4] : memref<4x4xf32, offset:?, strides: [64, 3]>
25 %1 = memref.load %0[%arg3, %arg4] : memref<4x4xf32, offset:?, strides: [?, ?]>
46 memref.store %arg5, %0[%arg3, %arg4] : memref<4x4xf32, offset:?, strides: [64, 3]>
66 memref.store %arg7, %0[%arg3, %arg4] : memref<4x4xf32, offset:?, strides: [?, ?]>
128 %arg3 : index, %arg4 : index, %arg5 : index, %arg6 : index,
168 %arg1: index, %arg2 : index, %arg3 : index, %arg4: index, %arg5 : index,
171 %0 = memref.subview %arg0[0, %arg1, %arg2] [1, %arg3, %arg4] [1, 1, 1]
197 %arg1 : vector<4xf32>, %arg2: index, %arg3 : index, %arg4 : index,
200 %0 = memref.subview %arg0[0, %arg2, %arg3] [1, %arg4, %arg5] [1, 1, 1]
227 %arg1 : vector<4xf32>, %arg2: index, %arg3 : index, %arg4 : index,
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/
H A Dkernel-args.ll7 ; CHECK: DIVERGENT: <3 x i32> %arg4
11 …]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %…
20 ; CHECK-NOT: %arg4
23 …]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %…
35 …]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %…
/llvm-project-15.0.7/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/
H A Dkernel-args.ll7 ; CHECK: DIVERGENT: <3 x i32> %arg4
11 …]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %…
20 ; CHECK-NOT: %arg4
23 …]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %…
35 …]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %…
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Damdgpu-abi-struct-coerce.cl453 void func_reg_state_hi(int4 arg0, int4 arg1, int4 arg2, int arg3, int arg4, struct_arg_t s) { }
477 void v3i32_reg_count(int3 arg1, int3 arg2, int3 arg3, int3 arg4, struct_arg_t arg5) { }
482 void v3i32_pair_reg_count(int3_pair *arg0, int3_pair arg1, int3 arg2, int3_pair arg3, int3 arg4, fl…
487 short4 arg4, short4 arg5, struct_4regs arg6) { }
491 short4 arg4, short4 arg5, short4 arg6, struct_4regs arg7) { }
495 short3 arg4, short3 arg5, struct_4regs arg6) { }
499 short3 arg4, short3 arg5, short3 arg6, struct_4regs arg7) { }
503 short2 arg4, short2 arg5, short2 arg6, short2 arg7,
509 short2 arg4, short2 arg5, short2 arg6, short2 arg7,
515 char2 arg4, char2 arg5, struct_4regs arg6) { }
[all …]
/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_win_dll_thunk.h156 extern "C" void *name(void *arg1, void *arg2, void *arg3, void *arg4) { \
159 return fn(arg1, arg2, arg3, arg4); \
164 extern "C" void *name(void *arg1, void *arg2, void *arg3, void *arg4, \
168 return fn(arg1, arg2, arg3, arg4, arg5); \
173 extern "C" void *name(void *arg1, void *arg2, void *arg3, void *arg4, \
177 return fn(arg1, arg2, arg3, arg4, arg5, arg6); \
H A Dsanitizer_syscall_linux_x86_64.inc47 static uptr internal_syscall(u64 nr, T1 arg1, T2 arg2, T3 arg3, T4 arg4) {
51 "S"((u64)arg2), "d"((u64)arg3), "r"((u64)arg4) :
57 static uptr internal_syscall(u64 nr, T1 arg1, T2 arg2, T3 arg3, T4 arg4,
63 "S"((u64)arg2), "d"((u64)arg3), "r"((u64)arg4), "r"((u64)arg5) :
70 static uptr internal_syscall(u64 nr, T1 arg1, T2 arg2, T3 arg3, T4 arg4,
77 "S"((u64)arg2), "d"((u64)arg3), "r"((u64)arg4), "r"((u64)arg5),
H A Dsanitizer_syscall_linux_loongarch64.inc76 u64 arg4) {
81 register u64 a3 asm("a3") = arg4;
91 static uptr __internal_syscall(u64 nr, u64 arg1, long arg2, long arg3, u64 arg4,
97 register u64 a3 asm("a3") = arg4;
109 static uptr __internal_syscall(u64 nr, u64 arg1, long arg2, long arg3, u64 arg4,
115 register u64 a3 asm("a3") = arg4;
128 static uptr __internal_syscall(u64 nr, u64 arg1, long arg2, long arg3, u64 arg4,
134 register u64 a3 asm("a3") = arg4;
H A Dsanitizer_syscall_linux_riscv64.inc83 u64 arg4) {
88 register u64 a3 asm("a3") = arg4;
98 static uptr __internal_syscall(u64 nr, u64 arg1, long arg2, long arg3, u64 arg4,
104 register u64 a3 asm("a3") = arg4;
116 static uptr __internal_syscall(u64 nr, u64 arg1, long arg2, long arg3, u64 arg4,
122 register u64 a3 asm("a3") = arg4;
135 static uptr __internal_syscall(u64 nr, u64 arg1, long arg2, long arg3, u64 arg4,
141 register u64 a3 asm("a3") = arg4;
/llvm-project-15.0.7/libc/src/__support/OSUtil/linux/aarch64/
H A Dsyscall.h26 register long x3 __asm__("x3") = arg4;
74 syscall(long number, long arg1, long arg2, long arg3, long arg4) { in syscall() argument
81 syscall(long number, long arg1, long arg2, long arg3, long arg4, long arg5) { in syscall() argument
89 long arg4, long arg5, in syscall() argument
/llvm-project-15.0.7/polly/test/CodeGen/
H A Dconflict-between-loop-invariant-code-hosting-and-escape-map-computation.ll11 define void @hoge(i8* %arg, i32 %arg4) #0 {
46 %tmp20 = phi i32 [ %tmp14, %bb13 ], [ %arg4, %bb18 ]
47 %tmp21 = phi i32 [ %tmp17, %bb13 ], [ %arg4, %bb18 ]
48 %tmp22 = phi i32 [ %tmp17b, %bb13 ], [ %arg4, %bb18 ]
/llvm-project-15.0.7/mlir/test/Transforms/
H A Dloop-fusion-3.mlir15 affine.for %arg4 = 0 to 3 {
20 affine.for %arg4 = 0 to 3 {
32 affine.for %arg4 = 0 to 3 {
234 affine.for %arg4 = 1 to 10 {
240 affine.for %arg4 = 1 to 10 {
360 affine.for %arg4 = 0 to 128 {
366 affine.for %arg4 = 0 to 512 {
806 affine.for %arg4 = 0 to 64 {
817 affine.for %arg4 = 0 to 64 {
865 affine.for %arg4 = 0 to 64 {
[all …]
/llvm-project-15.0.7/llvm/test/Verifier/ARM/
H A Dintrinsic-immarg.ll67 define void @mcrr(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
79 ; CHECK-NEXT: i32 %arg4
80 ; CHECK-NEXT: call void @llvm.arm.mcrr(i32 0, i32 1, i32 2, i32 3, i32 %arg4)
81 call void @llvm.arm.mcrr(i32 0, i32 1, i32 2, i32 3, i32 %arg4)
86 define void @mcrr2(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
98 ; CHECK-NEXT: i32 %arg4
99 ; CHECK-NEXT: call void @llvm.arm.mcrr2(i32 0, i32 1, i32 2, i32 3, i32 %arg4)
100 call void @llvm.arm.mcrr2(i32 0, i32 1, i32 2, i32 3, i32 %arg4)
/llvm-project-15.0.7/mlir/include/mlir/Dialect/MemRef/Transforms/
H A DPasses.td104 affine.for %arg4 = %c0 to %c8 {
107 %1 = affine.load %arg1[%arg5, %arg4] : memref<8x8xi32, #linear8>
108 %2 = affine.load %arg2[%arg3, %arg4] : memref<8x8xi32, #linear8>
111 affine.store %4, %arg2[%arg3, %arg4] : memref<8x8xi32, #linear8>
128 affine.for %arg4 = %c0 to %c8 {
131 %1 = affine.load %arg1[%arg5 * 8 + %arg4] : memref<64xi32>
132 %2 = affine.load %arg2[%arg3 * 8 + %arg4] : memref<64xi32>
135 affine.store %4, %arg2[%arg3 * 8 + %arg4] : memref<64xi32>
/llvm-project-15.0.7/mlir/test/Analysis/
H A Dtest-liveness.mlir298 %arg3 : i32, %arg4 : i32, %arg5 : i32,
317 // CHECK-SAME: arg0@0 arg1@0 arg2@0 arg3@0 arg4@0 arg5@0 arg6@0 val_7
319 // CHECK-SAME: arg0@0 arg1@0 arg2@0 arg4@0 arg5@0 arg6@0 val_7 val_8
328 %0 = arith.addi %arg3, %arg4 : i32
329 %1 = arith.addi %arg4, %arg5 : i32
385 %arg3 : i32, %arg4 : i32, %arg5 : i32,
387 %0 = arith.addi %arg3, %arg4 : i32
388 %1 = arith.addi %arg4, %arg5 : i32
452 %arg3 : i32, %arg4 : i32, %arg5 : i32,
454 %0 = arith.addi %arg3, %arg4 : i32
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dret.ll45 …inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <…
47 %i0 = extractelement <2 x i32> %arg4, i32 0
48 %i1 = extractelement <2 x i32> %arg4, i32 1
70 …inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <…
84 …inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <…
105 %i0 = extractelement <2 x i32> %arg4, i32 0
106 %i1 = extractelement <2 x i32> %arg4, i32 1
134 %i0 = extractelement <2 x i32> %arg4, i32 0
135 %i1 = extractelement <2 x i32> %arg4, i32 1
163 %i0 = extractelement <2 x i32> %arg4, i32 0
[all …]
/llvm-project-15.0.7/mlir/test/Conversion/SCFToSPIRV/
H A Dif.mlir29 func.func @kernel_nested_selection(%arg3 : memref<10xf32>, %arg4 : memref<10xf32>, %arg5 : i1, %arg…
65 memref.store %value, %arg4[%i] : memref<10xf32>
67 %value = memref.load %arg4[%i] : memref<10xf32>
73 memref.store %value, %arg4[%j] : memref<10xf32>
75 %value = memref.load %arg4[%j] : memref<10xf32>
127 func.func @simple_if_yield_type_change(%arg2 : memref<10xf32>, %arg3 : memref<10xf32>, %arg4 : i1) {
147 %0 = scf.if %arg4 -> (memref<10xf32>) {

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