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/llvm-project-15.0.7/mlir/test/Conversion/SPIRVToLLVM/
H A Dcomparison-ops-to-llvm.mlir10 %0 = spv.IEqual %arg0, %arg1 : i32
17 %0 = spv.IEqual %arg0, %arg1 : vector<4xi64>
28 %0 = spv.INotEqual %arg0, %arg1 : i64
64 %0 = spv.SGreaterThan %arg0, %arg1 : i64
82 %0 = spv.SLessThanEqual %arg0, %arg1 : i64
100 %0 = spv.SLessThan %arg0, %arg1 : i64
136 %0 = spv.UGreaterThan %arg0, %arg1 : i64
172 %0 = spv.ULessThan %arg0, %arg1 : i64
190 %0 = spv.FOrdEqual %arg0, %arg1 : f32
244 %0 = spv.FOrdLessThan %arg0, %arg1 : f64
[all …]
H A Darithmetic-ops-to-llvm.mlir10 %0 = spv.IAdd %arg0, %arg1 : i32
28 %0 = spv.ISub %arg0, %arg1 : i8
46 %0 = spv.IMul %arg0, %arg1 : i32
64 %0 = spv.FAdd %arg0, %arg1 : f16
82 %0 = spv.FSub %arg0, %arg1 : f32
100 %0 = spv.FDiv %arg0, %arg1 : f32
118 %0 = spv.FMul %arg0, %arg1 : f32
136 %0 = spv.FRem %arg0, %arg1 : f32
172 %0 = spv.UDiv %arg0, %arg1 : i32
190 %0 = spv.UMod %arg0, %arg1 : i32
[all …]
H A Dgl-ops-to-llvm.mlir12 %1 = spv.GL.Ceil %arg1 : vector<3xf16>
25 %1 = spv.GL.Cos %arg1 : vector<3xf16>
38 %1 = spv.GL.Exp %arg1 : vector<3xf16>
51 %1 = spv.GL.FAbs %arg1 : vector<3xf16>
64 %1 = spv.GL.Floor %arg1 : vector<3xf16>
77 %1 = spv.GL.FMax %arg1, %arg1 : vector<3xf16>
90 %1 = spv.GL.FMin %arg1, %arg1 : vector<3xf16>
103 %1 = spv.GL.Log %arg1 : vector<3xf16>
116 %1 = spv.GL.Sin %arg1 : vector<3xf16>
129 %1 = spv.GL.SMax %arg1, %arg1 : vector<3xi32>
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Tosa/
H A Dbroadcast.mlir7 %0 = "tosa.add"(%arg0, %arg1) : (tensor<1xf32>, tensor<1xf32>) -> tensor<1xf32>
15 // CHECK: %[[VAR1:.*]] = "tosa.add"(%[[VAR0]], %arg1)
23 // CHECK-DAG: %[[VAR0:.*]] = "tosa.reshape"(%arg1) {new_shape = [1, 1]}
105 // CHECK: %[[VAR1:.*]] = "tosa.add"(%[[VAR0]], %arg1)
114 // CHECK: %[[VAR1:.*]] = "tosa.add"(%[[VAR0]], %arg1)
123 // CHECK: %[[VAR1:.*]] = "tosa.add"(%[[VAR0]], %arg1)
132 // CHECK: %[[VAR1:.*]] = "tosa.add"(%[[VAR0]], %arg1)
141 // CHECK: %[[VAR1:.*]] = "tosa.add"(%[[VAR0]], %arg1)
149 // CHECK: %[[VAR1:.*]] = "tosa.add"(%arg0, %arg1)
176 // CHECK: %[[VAR1:.*]] = "tosa.mul"(%[[VAR0]], %arg1)
[all …]
H A Dtosa-infer-shapes.mlir16 %0 = "tosa.add"(%arg0, %arg1) : (tensor<4xf32>, tensor<1xf32>) -> tensor<*xf32>
121 %0 = "tosa.add"(%arg0, %arg1) : (tensor<4xf32>, tensor<f32>) -> tensor<*xf32>
133 %4 = "tosa.pow"(%arg0, %arg1) : (tensor<4xf32>, tensor<f32>) -> tensor<*xf32>
187 func.func @test_binary_i32(%arg0 : tensor<4xi32>, %arg1 : tensor<i32>) -> () {
236 func.func @test_binary_i1(%arg0 : tensor<4xi1>, %arg1 : tensor<i1>) -> () {
1045 %b = "tosa.log"(%arg1) : (tensor<f32>) -> tensor<*xf32>
1062 %0 = "tosa.cond_if"(%arg2, %arg0, %arg1) ({
1077 %0 = "tosa.cond_if"(%arg2, %arg0, %arg1) ({
1092 %0 = "tosa.cond_if"(%arg2, %arg0, %arg1) ({
1149 func.func @while_test(%arg0 : tensor<i32>, %arg1 : tensor<1xi32>) -> () {
[all …]
/llvm-project-15.0.7/flang/test/Lower/OpenMP/
H A Domp-parallel-lastprivate-clause-scalar.f9047 character(5) :: arg1 local
51 arg1(n:n) = 'c'
52 print *, arg1
74 integer :: arg1 local
78 arg1 = 2
79 print *, arg1
111 arg1 = 2
113 print *, arg1, arg2
142 arg1 = 2
144 print *, arg1, arg2
[all …]
/llvm-project-15.0.7/mlir/test/IR/
H A Dop-stats-json.mlir4 ^bb0(%arg0: tensor<4xf32>, %arg1: tensor<4xf32>):
5 %0 = arith.addf %arg0, %arg1 : tensor<4xf32>
6 %1 = arith.addf %arg0, %arg1 : tensor<4xf32>
7 %2 = arith.addf %arg0, %arg1 : tensor<4xf32>
8 %3 = arith.addf %arg0, %arg1 : tensor<4xf32>
9 %4 = arith.addf %arg0, %arg1 : tensor<4xf32>
10 %5 = arith.addf %arg0, %arg1 : tensor<4xf32>
11 %10 = "xla.add"(%0, %arg1) : (tensor<4xf32>,tensor<4xf32>)-> tensor<4xf32>
12 %11 = "xla.add"(%0, %arg1) : (tensor<4xf32>,tensor<4xf32>)-> tensor<4xf32>
13 %12 = "xla.add"(%0, %arg1) : (tensor<4xf32>,tensor<4xf32>)-> tensor<4xf32>
[all …]
H A Dop-stats.mlir4 ^bb0(%arg0: tensor<4xf32>, %arg1: tensor<4xf32>):
5 %0 = arith.addf %arg0, %arg1 : tensor<4xf32>
6 %1 = arith.addf %arg0, %arg1 : tensor<4xf32>
7 %2 = arith.addf %arg0, %arg1 : tensor<4xf32>
8 %3 = arith.addf %arg0, %arg1 : tensor<4xf32>
9 %4 = arith.addf %arg0, %arg1 : tensor<4xf32>
10 %5 = arith.addf %arg0, %arg1 : tensor<4xf32>
11 %10 = "xla.add"(%0, %arg1) : (tensor<4xf32>,tensor<4xf32>)-> tensor<4xf32>
12 %11 = "xla.add"(%0, %arg1) : (tensor<4xf32>,tensor<4xf32>)-> tensor<4xf32>
13 %12 = "xla.add"(%0, %arg1) : (tensor<4xf32>,tensor<4xf32>)-> tensor<4xf32>
[all …]
/llvm-project-15.0.7/mlir/test/Target/SPIRV/
H A Dlogical-ops.mlir6 %0 = spv.IEqual %arg0, %arg1 : i32
11 %0 = spv.INotEqual %arg0, %arg1 : vector<4xi32>
56 %1 = spv.FOrdEqual %arg0, %arg1 : f32
58 %2 = spv.FOrdGreaterThan %arg0, %arg1 : f32
62 %4 = spv.FOrdLessThan %arg0, %arg1 : f32
66 %6 = spv.FOrdNotEqual %arg0, %arg1 : f32
68 %7 = spv.FUnordEqual %arg0, %arg1 : f32
74 %10 = spv.FUnordLessThan %arg0, %arg1 : f32
80 %13 = spv.Ordered %arg0, %arg1 : f32
82 %14 = spv.Unordered %arg0, %arg1 : f32
[all …]
H A Darithmetic-ops.mlir4 spv.func @fmul(%arg0 : f32, %arg1 : f32) "None" {
6 %0 = spv.FMul %arg0, %arg1 : f32
11 %0 = spv.FAdd %arg0, %arg1 : vector<4xf32>
16 %0 = spv.FDiv %arg0, %arg1 : vector<4xf32>
21 %0 = spv.FMod %arg0, %arg1 : vector<4xf32>
31 %0 = spv.FSub %arg0, %arg1 : vector<4xf32>
36 %0 = spv.FRem %arg0, %arg1 : vector<4xf32>
41 %0 = spv.IAdd %arg0, %arg1 : vector<4xi32>
46 %0 = spv.ISub %arg0, %arg1 : vector<4xi32>
51 %0 = spv.IMul %arg0, %arg1 : vector<4xi32>
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Arithmetic/
H A Dops.mlir6 %0 = arith.addi %arg0, %arg1 : i64
30 %0 = arith.subi %arg0, %arg1 : i64
54 %0 = arith.muli %arg0, %arg1 : i64
78 %0 = arith.divui %arg0, %arg1 : i64
102 %0 = arith.divsi %arg0, %arg1 : i64
126 %0 = arith.remui %arg0, %arg1 : i64
150 %0 = arith.remsi %arg0, %arg1 : i64
174 %0 = arith.andi %arg0, %arg1 : i64
198 %0 = arith.ori %arg0, %arg1 : i64
222 %0 = arith.xori %arg0, %arg1 : i64
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/MemRef/
H A Dsubview.mlir45 // CHECK: memref.subview %4[%c0, %c1] [%arg0, %arg1] [%c1, %c0] :
48 %5 = memref.subview %4[%c0, %c1][%arg0, %arg1][%c1, %c0]
59 %7 = memref.alloc(%arg1, %arg2) : memref<?x?xf32>
70 %10 = memref.subview %9[%arg1, %arg1][4, 4][%arg2, %arg2]
76 %11 = memref.subview %9[%arg1, %arg2][4, 4][2, 2]
80 // CHECK: memref.subview %12[%arg1, %arg1, %arg1, %arg1, %arg1]
83 …%13 = memref.subview %12[%arg1, %arg1, %arg1, %arg1, %arg1][1, 9, 1, 4, 1][%arg2, %arg2, %arg2, %a…
84 // CHECK: memref.subview %12[%arg1, %arg1, %arg1, %arg1, %arg1]
87 …%14 = memref.subview %12[%arg1, %arg1, %arg1, %arg1, %arg1][1, 9, 1, 4, 1][%arg2, %arg2, %arg2, %a…
93 …// CHECK: memref.subview %15[%arg1, %arg1, %arg1, %arg1, %arg1, %arg1] [1, %arg1, 5, 1, %arg2, 1] …
[all …]
/llvm-project-15.0.7/polly/test/CodeGen/
H A Dregion_multiexit_partialwrite___%bb3---%bb19.jscop.transformed18 "context": "[arg1] -> { : -9223372036854775808 <= arg1 <= 9223372036854775807 }",
25 "relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_arg[1 + i0] }"
29 …"relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_arg2[1 + i0] : arg1 <= 23058430092136939…
32 "domain": "[arg1] -> { Stmt_bb3__TO__bb10[i0] : 0 <= i0 <= -2 + arg1 }",
34 "schedule": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> [i0, 0] }"
40 "relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_arg2[1 + i0] }"
44 "relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_arg2[1 + i0] }"
47 "domain": "[arg1] -> { Stmt_bb10[i0] : 0 <= i0 <= -2 + arg1 }",
49 "schedule": "[arg1] -> { Stmt_bb10[i0] -> [i0, 1] }"
H A Dregion_multiexit_partialwrite___%bb3---%bb19.jscop18 "context": "[arg1] -> { : -9223372036854775808 <= arg1 <= 9223372036854775807 }",
25 "relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_arg[1 + i0] }"
29 "relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_tmp11__phi[] }"
32 "domain": "[arg1] -> { Stmt_bb3__TO__bb10[i0] : 0 <= i0 <= -2 + arg1 }",
34 "schedule": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> [i0, 0] }"
40 "relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_tmp11__phi[] }"
44 "relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_arg2[1 + i0] }"
47 "domain": "[arg1] -> { Stmt_bb10[i0] : 0 <= i0 <= -2 + arg1 }",
49 "schedule": "[arg1] -> { Stmt_bb10[i0] -> [i0, 1] }"
/llvm-project-15.0.7/mlir/test/Dialect/
H A Dtraits.mlir7 ^bb0(%arg0: tensor<i32>, %arg1: tensor<i32>):
15 ^bb0(%arg0: tensor<4xi32>, %arg1: tensor<i32>):
24 ^bb0(%arg0: tensor<4x3x2xi32>, %arg1: tensor<3x1xi32>):
60 ^bb0(%arg0: tensor<4xf32>, %arg1: tensor<4xf32>):
70 ^bb0(%arg0: tensor<4x3x2xi32>, %arg1: tensor<3x3xi32>):
99 ^bb0(%arg0: tensor<2xi32>, %arg1: tensor<2xi32>):
107 ^bb0(%arg0: tensor<4x3x2xi32>, %arg1: tensor<?xi32>):
123 ^bb0(%arg0: tensor<*xi32>, %arg1: tensor<*xi32>):
132 ^bb0(%arg0: tensor<3x2xi32>, %arg1: tensor<*xi32>):
140 ^bb0(%arg0: tensor<3x2xi32>, %arg1: tensor<*xi32>):
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-shift-of-shifted-logic.ll10 %z1 = shl i32 %arg1, 2
22 %z1 = shl i32 %arg1, 5
35 %z1 = shl i32 %arg1, 3
47 %z1 = lshr i32 %arg1, 2
60 %z1 = lshr i32 %arg1, 5
72 %z1 = lshr i32 %arg1, 3
85 %z1 = ashr i32 %arg1, 2
98 %z1 = ashr i32 %arg1, 5
124 %z1 = shl i32 %arg1, 2
137 %z1 = shl i32 %arg1, 3
[all …]
/llvm-project-15.0.7/mlir/test/Conversion/ArithmeticToLLVM/
H A Darith-to-llvm.mlir40 %0 = arith.subf %arg0, %arg1: f32
54 %8 = arith.divf %arg0, %arg1 : f32
56 %9 = arith.remf %arg0, %arg1 : f32
103 %2 = arith.sitofp %arg1: i64 to f32
105 %3 = arith.sitofp %arg1: i64 to f64
135 %2 = arith.uitofp %arg1: i64 to f32
137 %3 = arith.uitofp %arg1: i64 to f64
149 %2 = arith.extf %arg1: f32 to f64
173 %2 = arith.fptosi %arg1: f64 to i32
175 %3 = arith.fptosi %arg1: f64 to i64
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dsub-vec.ll9 %ret = sub <16 x i8> %arg1, %arg2
18 %ret = sub <8 x i16> %arg1, %arg2
27 %ret = sub <4 x i32> %arg1, %arg2
36 %ret = sub <2 x i64> %arg1, %arg2
45 %ret = sub <32 x i8> %arg1, %arg2
54 %ret = sub <16 x i16> %arg1, %arg2
63 %ret = sub <8 x i32> %arg1, %arg2
72 %ret = sub <4 x i64> %arg1, %arg2
81 %ret = sub <64 x i8> %arg1, %arg2
90 %ret = sub <32 x i16> %arg1, %arg2
[all …]
H A Dmul-vec.ll4 define <8 x i16> @test_mul_v8i16(<8 x i16> %arg1, <8 x i16> %arg2) {
9 %ret = mul <8 x i16> %arg1, %arg2
13 define <4 x i32> @test_mul_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
18 %ret = mul <4 x i32> %arg1, %arg2
27 %ret = mul <2 x i64> %arg1, %arg2
36 %ret = mul <16 x i16> %arg1, %arg2
45 %ret = mul <8 x i32> %arg1, %arg2
54 %ret = mul <4 x i64> %arg1, %arg2
63 %ret = mul <32 x i16> %arg1, %arg2
72 %ret = mul <16 x i32> %arg1, %arg2
[all …]
H A Dshl-scalar.ll12 %res = shl i64 %arg1, %arg2
22 %res = shl i64 %arg1, 5
31 %res = shl i64 %arg1, 1
43 %res = shl i32 %arg1, %arg2
53 %res = shl i32 %arg1, 5
63 %res = shl i32 %arg1, 1
76 %a = trunc i32 %arg1 to i16
89 %a = trunc i32 %arg1 to i16
115 %a = trunc i32 %arg1 to i8
128 %a = trunc i32 %arg1 to i8
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Math/
H A Dalgebraic-simplification.mlir5 // CHECK: return %arg0, %arg1
9 %1 = math.powf %arg1, %v : vector<4xf32>
16 // CHECK: %[[VECTOR:.*]] = arith.mulf %arg1, %arg1
21 %1 = math.powf %arg1, %v : vector<4xf32>
29 // CHECK: %[[TMP_V:.*]] = arith.mulf %arg1, %arg1
35 %1 = math.powf %arg1, %v : vector<4xf32>
49 %1 = math.powf %arg1, %v : vector<4xf32>
56 // CHECK: %[[VECTOR:.*]] = math.sqrt %arg1
61 %1 = math.powf %arg1, %v : vector<4xf32>
68 // CHECK: %[[VECTOR:.*]] = math.rsqrt %arg1
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/SPIRV/IR/
H A Dlogical-ops.mlir7 func.func @iequal_scalar(%arg0: i32, %arg1: i32) -> i1 {
9 %0 = spv.IEqual %arg0, %arg1 : i32
17 %0 = spv.IEqual %arg0, %arg1 : vector<4xi32>
29 %0 = spv.INotEqual %arg0, %arg1 : vector<4xi32>
76 %0 = spv.LogicalAnd %arg0, %arg1 : i1
91 func.func @logicalBinary(%arg0 : i1, %arg1 : i1)
94 %0 = spv.LogicalAnd %arg0, %arg1
100 func.func @logicalBinary(%arg0 : i1, %arg1 : i1)
103 %0 = spv.LogicalAnd %arg0, %arg1 :
109 func.func @logicalBinary(%arg0 : i1, %arg1 : i1)
[all …]
/llvm-project-15.0.7/libc/test/src/stdio/printf_core/
H A Dparser_test.cpp88 int arg1 = 12345; in TEST() local
104 int arg1 = 12345; in TEST() local
126 int arg1 = 12345; in TEST() local
143 int arg1 = 12345; in TEST() local
160 int arg1 = 12345; in TEST() local
177 int arg1 = 12345; in TEST() local
194 int arg1 = 12345; in TEST() local
211 int arg1 = 12345; in TEST() local
234 int arg1 = 12345; in TEST() local
270 int arg1 = 12345; in TEST() local
[all …]
/llvm-project-15.0.7/mlir/test/Analysis/
H A Dtest-liveness.mlir21 // CHECK-NEXT: LiveOut: arg0@0 arg1@0
26 // CHECK-SAME: arg0@0 arg1@0
31 // CHECK-NEXT: LiveIn: arg0@0 arg1@0
69 // CHECK-SAME: arg1@0 arg2@0
78 // CHECK-SAME: arg1@0 arg2@0
106 // CHECK-NEXT: LiveOut: arg1@0
117 // CHECK-NEXT: LiveIn: arg1@0
126 // CHECK-SAME: arg1@0 arg0@1 arg1@1 val_5
128 // CHECK-SAME: arg1@0 arg0@1 arg1@1 val_5
135 // CHECK-NEXT: LiveOut: arg1@0
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dext-narrow-index.ll184 define <8 x i8> @i8_zero_off0(<16 x i8> %arg1) {
194 define <8 x i8> @i8_zero_off1(<16 x i8> %arg1) {
205 define <8 x i8> @i8_zero_off8(<16 x i8> %arg1) {
216 define <8 x i8> @i8_zero_off15(<16 x i8> %arg1) {
228 define <8 x i8> @i8_zero_off22(<16 x i8> %arg1) {
239 define <4 x i16> @i16_zero_off0(<8 x i16> %arg1) {
249 define <4 x i16> @i16_zero_off1(<8 x i16> %arg1) {
260 define <4 x i16> @i16_zero_off7(<8 x i16> %arg1) {
272 define <4 x i16> @i16_zero_off8(<8 x i16> %arg1) {
283 define <2 x i32> @i32_zero_off0(<4 x i32> %arg1) {
[all …]

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