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/llvm-project-15.0.7/llvm/test/TableGen/
H A DGlobalISelEmitterSubreg.td46 // SKIPPED: def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), i16:$src, sub0)…
47 // SKIPPED: def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF)), i16:…
48 def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), i16:$src, sub0)>;
49 def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF)), i16:$src, sub0))…
53 def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SOP:$src, sub0)>;
54 // CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (INSERT_SUBREG:{ *:[i32] } (IMPLICI…
72 def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SOP:$src, sub0))…
73 // CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (SOME_INSN:{ *:[i32] } (INSERT_SUBR…
97 def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (COPY_TO_REGCLASS SOP:$src, ERegs)), SOP:$sr…
106 def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (SUBSOME_INSN SOP:$src), su…
[all …]
H A DGlobalISelEmitter-nested-subregs.td40 // CHECK-NEXT: // (anyext:{ *:[i16] } i8:{ *:[i8] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (INSERT_…
60 def : Pat<(i16 (anyext i8:$src)),
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dmem64.ll5 ; Check indexed and unindexed, sext, zext and anyext loads
17 ; the unused load will produce an anyext for selection
32 ; the unused load will produce an anyext for selection
47 ; the unused load will produce an anyext for selection
183 ; extload i1 (anyext). Produced as the load is unused.
205 ; extload i1 (anyext). Produced as the load is unused.
H A Dmem.ll5 ; Check indexed and unindexed, sext, zext and anyext loads
17 ; the unused load will produce an anyext for selection
32 ; the unused load will produce an anyext for selection
138 ; extload i1 (anyext). Produced as the load is unused.
160 ; extload i1 (anyext). Produced as the load is unused.
H A Daext-to-sext.ll7 ; setcc use using signext and the phi use using anyext.
9 ; anyext with signext.
H A Dcalling-conv-lp64.ll15 ; TODO: softened float values can be passed anyext.
172 ; passed anyext.
H A Drv32i-rv64i-float-double.ll12 ; TODO: f32 parameters on RV64 with a soft-float ABI are anyext.
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dno-wide-load.ll2 ; RUN: llc < %s -mtriple=x86_64-- -x86-promote-anyext-load=false | FileCheck %s
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dprelegalizercombiner-hoist-same-hands.mir61 ; or (anyext X), (anyext Y) --> anyext (or X, Y)
136 ; and (anyext X), (anyext Y) --> anyext (and X, Y)
211 ; xor (anyext X), (anyext Y) --> anyext (xor X, Y)
H A Dpostlegalizercombiner-extending-loads.mir39 ; Check that we don't try to do an anyext combine. We don't want to do this
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DKnownBits.h158 KnownBits anyext(unsigned BitWidth) const { in anyext() function
179 return anyext(BitWidth); in anyextOrTrunc()
H A DTargetOpcodes.def53 /// anyext operations on target architectures which support it.
343 /// Generic load (including anyext load)
352 /// Generic indexed load (including anyext load)
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrData.td559 // i16 <- anyext i8
560 def: Pat<(i16 (anyext i8:$src)),
569 // i32 <- anyext i8
570 def: Pat<(i32 (anyext i8:$src)), (MOVZXd32d8 MxDRD8:$src)>;
575 // i32 <- anyext i16
576 def: Pat<(i32 (anyext i16:$src)), (MOVZXd32d16 MxDRD16:$src)>;
H A DM68kInstrControl.td327 def : Pat<(i16 (anyext (i8 (MxSetCC_C MxCONDcs, CCR)))), (SETCS_C16d)>;
328 def : Pat<(i32 (anyext (i8 (MxSetCC_C MxCONDcs, CCR)))), (SETCS_C32d)>;
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrAtomics.td264 // i64 (and (i64 (anyext (i32 (atomic_load_8)))), 255)
278 // match bare subword loads (for 32-bit results) and anyext loads (for 64-bit
282 PatFrag<(ops node:$addr), (anyext (i32 (atomic_load_8 node:$addr)))>;
284 PatFrag<(ops node:$addr), (anyext (i32 (atomic_load_16 node:$addr)))>;
648 // load patterns above. We match subword RMWs (for 32-bit) and anyext RMWs (for
656 (anyext (i32 (kind node:$addr, (i32 (trunc (i64 node:$val))))))>;
862 // additional nodes such as anyext or assertzext depending on operand types.
880 // We match subword RMWs (for 32-bit) and anyext RMWs (for 64-bit) and select a
889 (anyext (i32 (assertzext (i32
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Dconv.ll276 ; If the high bits are unused, LLVM will optimize sext/zext into anyext, which
279 ; CHECK-LABEL: anyext:
281 define i64 @anyext(i32 %x) {
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/ir-instruction/
H A Dload-store.ll75 ;; Check indexed and unindexed, sext, zext and anyext loads.
315 ;; extload i1 (anyext). Produced as the load is unused.
345 ;; extload i1 (anyext). Produced as the load is unused.
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPatterns.td2935 /*anyext*/ L4_add_memopb_io>;
2941 /*anyext*/ L4_add_memoph_io>;
2950 /*anyext*/ L4_sub_memopb_io>;
2956 /*anyext*/ L4_sub_memoph_io>;
2965 /*anyext*/ L4_and_memopb_io>;
2971 /*anyext*/ L4_and_memoph_io>;
2980 /*anyext*/ L4_or_memopb_io>;
2986 /*anyext*/ L4_or_memoph_io>;
3036 /*anyext*/ IdImm, L4_iadd_memopb_io>;
3042 /*anyext*/ IdImm, L4_iadd_memoph_io>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrCompiler.td1390 // anyext. Define these to do an explicit zero-extend to
1392 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1394 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1397 def : Pat<(i32 (anyext GR16:$src)),
1400 def : Pat<(i64 (anyext GR8 :$src)),
1402 def : Pat<(i64 (anyext GR16:$src)),
1404 def : Pat<(i64 (anyext GR32:$src)),
1411 def anyext_sdiv : PatFrag<(ops node:$lhs), (anyext node:$lhs),[{
1437 def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)),
1734 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td4817 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))),
4819 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))),
4821 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 2)))),
4823 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 3)))),
4825 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 4)))),
4827 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 5)))),
4829 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 6)))),
4831 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 7)))),
4953 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))),
4955 def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))),
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dbitfield.ll188 ; making sure that a 64-bit "(sext_inreg (anyext GPR32), i1)" uses the 64-bit
/llvm-project-15.0.7/llvm/include/llvm/Target/GlobalISel/
H A DSelectionDAGCompat.td45 def : GINodeEquiv<G_ANYEXT, anyext>;
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.td1732 def : Pat<(i64 (anyext i32:$sy)),
1816 def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRrri:$addr))), TY)),
1818 def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRrii:$addr))), TY)),
1820 def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRzri:$addr))), TY)),
1822 def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRzii:$addr))), TY)),
1846 def : Pat<(i64 (and (anyext (from ADDRrri:$addr)), VAL)),
1848 def : Pat<(i64 (and (anyext (from ADDRrii:$addr)), VAL)),
1850 def : Pat<(i64 (and (anyext (from ADDRzri:$addr)), VAL)),
1852 def : Pat<(i64 (and (anyext (from ADDRzii:$addr)), VAL)),
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstr64Bit.td20 // This give us free trunc and anyext.
21 def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Darguments.ll142 ; anyext from i8 and align 8 on it.

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