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/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dcond-store-02.ll9 define void @f1(i16 *%ptr, i16 %alt, i32 %limit) {
18 %res = select i1 %cond, i16 %orig, i16 %alt
33 %res = select i1 %cond, i16 %alt, i16 %orig
50 %res = select i1 %cond, i32 %ext, i32 %alt
67 %res = select i1 %cond, i32 %alt, i32 %ext
85 %res = select i1 %cond, i32 %ext, i32 %alt
102 %res = select i1 %cond, i32 %alt, i32 %ext
120 %res = select i1 %cond, i64 %ext, i64 %alt
137 %res = select i1 %cond, i64 %alt, i64 %ext
155 %res = select i1 %cond, i64 %ext, i64 %alt
[all …]
H A Dcond-store-01.ll9 define void @f1(i8 *%ptr, i8 %alt, i32 %limit) {
18 %res = select i1 %cond, i8 %orig, i8 %alt
24 define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
33 %res = select i1 %cond, i8 %alt, i8 %orig
50 %res = select i1 %cond, i32 %ext, i32 %alt
67 %res = select i1 %cond, i32 %alt, i32 %ext
85 %res = select i1 %cond, i32 %ext, i32 %alt
102 %res = select i1 %cond, i32 %alt, i32 %ext
120 %res = select i1 %cond, i64 %ext, i64 %alt
189 %res = select i1 %cond, i8 %orig, i8 %alt
[all …]
H A Dcond-store-03.ll8 define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
17 %res = select i1 %cond, i32 %orig, i32 %alt
23 define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
32 %res = select i1 %cond, i32 %alt, i32 %orig
49 %res = select i1 %cond, i64 %ext, i64 %alt
66 %res = select i1 %cond, i64 %alt, i64 %ext
84 %res = select i1 %cond, i64 %ext, i64 %alt
101 %res = select i1 %cond, i64 %alt, i64 %ext
118 %res = select i1 %cond, i32 %orig, i32 %alt
134 %res = select i1 %cond, i32 %orig, i32 %alt
[all …]
H A Dcond-store-05.ll8 define void @f1(float *%ptr, float %alt, i32 %limit) {
17 %res = select i1 %cond, float %orig, float %alt
23 define void @f2(float *%ptr, float %alt, i32 %limit) {
32 %res = select i1 %cond, float %alt, float %orig
48 %res = select i1 %cond, float %orig, float %alt
64 %res = select i1 %cond, float %orig, float %alt
80 %res = select i1 %cond, float %orig, float %alt
98 %res = select i1 %cond, float %orig, float %alt
114 %res = select i1 %cond, float %orig, float %alt
132 %res = select i1 %cond, float %orig, float %alt
[all …]
H A Dcond-store-06.ll8 define void @f1(double *%ptr, double %alt, i32 %limit) {
17 %res = select i1 %cond, double %orig, double %alt
23 define void @f2(double *%ptr, double %alt, i32 %limit) {
32 %res = select i1 %cond, double %alt, double %orig
48 %res = select i1 %cond, double %orig, double %alt
64 %res = select i1 %cond, double %orig, double %alt
80 %res = select i1 %cond, double %orig, double %alt
98 %res = select i1 %cond, double %orig, double %alt
114 %res = select i1 %cond, double %orig, double %alt
132 %res = select i1 %cond, double %orig, double %alt
[all …]
H A Dcond-store-04.ll8 define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
17 %res = select i1 %cond, i64 %orig, i64 %alt
23 define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
32 %res = select i1 %cond, i64 %alt, i64 %orig
48 %res = select i1 %cond, i64 %orig, i64 %alt
66 %res = select i1 %cond, i64 %orig, i64 %alt
82 %res = select i1 %cond, i64 %orig, i64 %alt
100 %res = select i1 %cond, i64 %orig, i64 %alt
118 %res = select i1 %cond, i64 %orig, i64 %alt
133 %res = select i1 %cond, i64 %orig, i64 %alt
[all …]
H A Dcond-store-07.ll12 define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
19 %res = select i1 %cond, i32 %orig, i32 %alt
32 %res = select i1 %cond, i32 %alt, i32 %orig
47 %res = select i1 %cond, i64 %ext, i64 %alt
62 %res = select i1 %cond, i64 %alt, i64 %ext
78 %res = select i1 %cond, i64 %ext, i64 %alt
93 %res = select i1 %cond, i64 %alt, i64 %ext
108 %res = select i1 %cond, i32 %orig, i32 %alt
123 %res = select i1 %cond, i32 %orig, i32 %alt
137 %res = select i1 %cond, i32 %orig, i32 %alt
[all …]
H A Dcond-store-08.ll8 define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
15 %res = select i1 %cond, i64 %orig, i64 %alt
21 define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
28 %res = select i1 %cond, i64 %alt, i64 %orig
34 define void @f3(i64 *%base, i64 %alt, i32 %limit) {
42 %res = select i1 %cond, i64 %orig, i64 %alt
57 %res = select i1 %cond, i64 %orig, i64 %alt
71 %res = select i1 %cond, i64 %orig, i64 %alt
86 %res = select i1 %cond, i64 %orig, i64 %alt
92 define void @f7(i64 %alt, i32 %limit) {
[all …]
H A Dcond-store-09.ll16 %alt = call i32 asm "stepa $0", "=h"()
19 %res = select i1 %cond, i32 %orig, i32 %alt
31 %alt = call i32 asm "stepa $0", "=h"()
34 %res = select i1 %cond, i32 %alt, i32 %orig
46 %alt = call i32 asm "stepa $0", "=h"()
50 %res = select i1 %cond, i32 %orig, i32 %alt
63 %alt = call i32 asm "stepa $0", "=h"()
67 %res = select i1 %cond, i32 %orig, i32 %alt
79 %alt = call i32 asm "stepa $0", "=h"()
96 %alt = call i32 asm "stepa $0", "=h"()
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/ScalarEvolution/
H A Dunsimplified-loop.ll6 ; CHECK: %i = phi i64 [ 5, %entry ], [ 5, %alt ], [ %i.next, %loop.a ], [ %i.next, %loop.b ]
11 br i1 %p, label %loop, label %alt
13 alt:
17 %i = phi i64 [ 5, %entry ], [ 5, %alt ], [ %i.next, %loop.a ], [ %i.next, %loop.b ]
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_mips.h33 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3) \ argument
35 #reg, alt, sizeof(((GPR_linux_mips *) NULL)->reg) / 2, \
47 #define DEFINE_FPR(reg, alt, kind1, kind2, kind3) \ argument
49 #reg, alt, sizeof(((FPR_linux_mips *) NULL)->reg), \
57 #define DEFINE_FPR_INFO(reg, alt, kind1, kind2, kind3) \ argument
59 #reg, alt, sizeof(((FPR_linux_mips *) NULL)->reg), \
66 #define DEFINE_MSA(reg, alt, kind1, kind2, kind3, kind4) \ argument
68 #reg, alt, sizeof(((MSA_linux_mips *) 0)->reg), \
75 #define DEFINE_MSA_INFO(reg, alt, kind1, kind2, kind3, kind4) \ argument
77 #reg, alt, sizeof(((MSA_linux_mips *) 0)->reg), \
H A DRegisterInfos_mips64.h27 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \ argument
29 #reg, alt, sizeof(((GPR_freebsd_mips *) 0)->reg), \
36 #define DEFINE_FPR(reg, alt, kind1, kind2, kind3) \ argument
38 #reg, alt, sizeof(((FPR_freebsd_mips *) 0)->reg), \
45 #define DEFINE_FPR_INFO(reg, alt, kind1, kind2, kind3) \ argument
47 #reg, alt, sizeof(((FPR_freebsd_mips *) 0)->reg), \
H A DRegisterInfos_s390x.h25 #define DEFINE_GPR(name, size, offset, alt, generic) \ argument
27 #name, alt, size, offset, eEncodingUint, eFormatHex, \
33 #define DEFINE_GPR_NODWARF(name, size, offset, alt, generic) \ argument
35 #name, alt, size, offset, eEncodingUint, eFormatHex, \
H A DRegisterContextWindows_i386.cpp39 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \ argument
41 #reg, alt, sizeof(((GPR *)nullptr)->reg), GPR_OFFSET(reg), eEncodingUint, \
H A DRegisterInfos_ppc64.h25 #define DEFINE_GPR_PPC64(reg, alt, lldb_kind) \ argument
27 #reg, alt, GPR_PPC64_SIZE(reg), GPR_PPC64_OFFSET(reg), lldb::eEncodingUint,\
36 #define DEFINE_FPR_PPC64(reg, alt, lldb_kind) \ argument
38 #reg, alt, 8, FPR_PPC64_OFFSET(reg), lldb::eEncodingIEEE754, \
/llvm-project-15.0.7/clang-tools-extra/pseudo/tool/
H A DHTMLForest.js127 var alt = document.createElement('div');
128 alt.classList.add('alternative');
129 alt.innerText = text;
130 alt.dataset['index'] = i;
131 alt.dataset['parent'] = that.index;
133 alt.classList.add('selected');
134 alternatives.appendChild(alt);
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.td13 class MSP430Reg<bits<4> num, string n, list<string> alt = []> : Register<n> {
17 let AltNames = alt;
22 list<string> alt = []>
27 let AltNames = alt;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td28 list<string> alt = []> :
30 let AltNames = alt;
41 list<string> alt = []> :
43 let AltNames = alt;
50 HexagonReg<num, n, alt>;
64 list<string> alt = []> :
81 HexagonReg<num, n, alt, alias>;
85 list<string> alt = []> :
93 HexagonSys<num, n, alt, alias>;
97 list<string> alt = []> :
[all …]
/llvm-project-15.0.7/llvm/include/llvm/ADT/
H A DOptional.h318 template <typename U> constexpr T value_or(U &&alt) const & { in value_or() argument
319 return has_value() ? value() : std::forward<U>(alt); in value_or()
323 getValueOr(U &&alt) const & { in getValueOr() argument
324 return has_value() ? value() : std::forward<U>(alt); in getValueOr()
339 template <typename U> T value_or(U &&alt) && { in value_or() argument
340 return has_value() ? std::move(value()) : std::forward<U>(alt); in value_or()
343 [[deprecated("Use value_or instead.")]] T getValueOr(U &&alt) && { in getValueOr() argument
344 return has_value() ? std::move(value()) : std::forward<U>(alt); in getValueOr()
/llvm-project-15.0.7/lldb/source/Plugins/Process/Windows/Common/x86/
H A DRegisterContextWindows_x86.cpp28 #define DEFINE_GPR(reg, alt) #reg, alt, 4, 0, eEncodingUint, eFormatHexUppercase argument
29 #define DEFINE_GPR_BIN(reg, alt) #reg, alt, 4, 0, eEncodingUint, eFormatBinary argument
/llvm-project-15.0.7/llvm/test/Transforms/Coroutines/
H A Dcoro-spill-after-phi.ll34 br i1 %n, label %begin, label %alt
35 alt:
39 %phi1 = phi i32 [ 0, %entry ], [ 2, %alt ]
40 %phi2 = phi i32 [ 1, %entry ], [ 3, %alt ]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td14 class LoongArchReg<bits<16> Enc, string n, list<string> alt = []>
17 let AltNames = alt;
20 class LoongArchReg32<bits<16> Enc, string n, list<string> alt = []>
23 let AltNames = alt;
/llvm-project-15.0.7/llvm/test/TableGen/
H A DAllowDuplicateRegisterNames.td22 class ArchReg<string n, list <string> alt, list <RegAltNameIndex> altidx>
24 let AltNames = alt;
/llvm-project-15.0.7/llvm/test/ExecutionEngine/JITLink/X86/
H A DELF_x86-64_small_pic_relocations.s62 # jitlink-check: (section_addr(elf_sm_pic_reloc.o, .text.alt) + 16) - \
158 .section .text.alt,"ax",@progbits
160 # 16 within .text.alt.
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td14 class CSKYReg<bits<6> Enc, string n, list<string> alt = []> : Register<n> {
16 let AltNames = alt;
19 class CSKYFReg32<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
21 let AltNames = alt;

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