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Searched refs:active (Results 1 – 25 of 219) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Analysis/CostModel/RISCV/
H A D	active_lane_mask.ll	62 declare <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i64(i64, i64) 73 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64, i64) 74 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64, i64) 75 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64, i64) 76 declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64, i64) 77 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32) 78 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32) 79 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) 80 declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32, i32) 81 declare <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64, i64) [all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/ARM/
H A D	active_lane_mask.ll	38 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64, i64) 39 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64, i64) 40 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64, i64) 41 declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64, i64) 42 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32) 43 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32) 44 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) 45 declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32, i32) 47 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i16(i16, i16) 48 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i16(i16, i16) [all …]
H A D	mve-active_lane_mask.ll	7 ; predicated) should not really be free. We currently assume that all active 12 …del: Found an estimated cost of 0 for instruction: %active.lane.mask = call <4 x i1> @llvm.get.act… 15 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %TC) 21 …del: Found an estimated cost of 0 for instruction: %active.lane.mask = call <8 x i1> @llvm.get.act… 24 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %TC) 30 …el: Found an estimated cost of 0 for instruction: %active.lane.mask = call <16 x i1> @llvm.get.act… 33 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %TC) 37 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) 38 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32) 39 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A D	active_lane_mask.ll	11 …%active.lane.mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 %index, i32… 20 …%active.lane.mask = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32 %index, i32 %… 29 …%active.lane.mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 %index, i32 %… 344 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %TC) 355 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %TC) 366 %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %TC) 388 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 %index, i64 %TC) 424 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i8(i8 %index, i8 %TC) 438 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i8(i8 %index, i8 %TC) 456 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i8(i8 %index, i8 %TC) [all …]
/llvm-project-15.0.7/llvm/test/Analysis/Lint/
H A D	get-active-lane-mask.ll	6 ; CHECK-NEXT: %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 0) 8 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 0) 15 ; CHECK-NOT: call <4 x i1> @llvm.get.active.lane.mask 17 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 1) 24 ; CHECK-NOT: call <4 x i1> @llvm.get.active.lane.mask 26 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 -1) 33 ; CHECK-NOT: call <4 x i1> @llvm.get.active.lane.mask 35 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 %TC) 39 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/ConstProp/
H A D	active-lane-mask.ll	12 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 0) 22 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 1) 32 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 8) 42 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 15) 104 %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 0) 114 %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 1) 124 %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 4) 134 %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 7) 304 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) 305 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32) [all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A D	tail-pred-basic.ll	32 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %N) 80 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N) 128 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N) 175 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N) 233 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N) 289 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N) 350 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N) 352 %active.lane.mask15 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %v7, i32 %N) 354 %active.lane.mask16 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %v8, i32 %N) 356 %active.lane.mask17 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %v9, i32 %N) [all …]
H A D	constbound.ll	40 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 500) 44 %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer 77 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 501) 81 %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer 114 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 502) 118 %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer 151 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 503) 155 %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer 188 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 504) 192 %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer [all …]
H A D	tail-pred-intrinsic-round.ll	35 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n) 40 …llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask) 80 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n) 85 …llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask) 125 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n) 130 …llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask) 170 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n) 175 …llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask) 215 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n) 264 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n) [all …]
H A D	tail-pred-intrinsic-add-sat.ll	37 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize) 39 …8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i1… 41 …8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i1… 44 …call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.la… 86 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize) 88 …8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i1… 90 …8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i1… 93 …call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.la… 102 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
H A D	tail-pred-intrinsic-sub-sat.ll	37 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize) 39 …8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i1… 41 …8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i1… 44 …call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.la… 86 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize) 88 …8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i1… 90 …8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i1… 93 …call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.la… 102 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
H A D	reductions.ll	39 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %N) 107 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N) 178 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %N) 247 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N) 318 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %N) 387 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N) 483 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N) 512 %active.lane.mask61 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index51, i32 %N) 595 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N) 719 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %4) [all …]
H A D	tp-multiple-vpst.ll	`35 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 10) 37 …4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %1, i32 4, <4 x i1> %active.lane.mask, <4 x i3… 40 %4 = and <4 x i1> %active.lane.mask, %3 42 %6 = and <4 x i1> %active.lane.mask, %2 55 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) #1`
/llvm-project-15.0.7/llvm/test/Verifier/
H A D	get-active-lane-mask.ll	`3 declare <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32, i32) 7 ; CHECK-NEXT: %res = call <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32 %IV, i32 %TC) 9 %res = call <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32 %IV, i32 %TC) 13 declare i32 @llvm.get.active.lane.mask.i32.i32(i32, i32) 17 ; CHECK-NEXT: ptr @llvm.get.active.lane.mask.i32.i32 19 %res = call i32 @llvm.get.active.lane.mask.i32.i32(i32 %IV, i32 %TC)`
/llvm-project-15.0.7/libcxx/test/support/
H A D	format_string.h	`15 bool active; in format_string_imp() member 16 GuardVAList(va_list& val) : xtarget(val), active(true) {} in format_string_imp() 19 if (active) in format_string_imp() 21 active = false; in format_string_imp() 24 if (active) in format_string_imp()`
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/ARM/
H A D	tail-folding-prefer-flag.ll	25 ; PREDFLAG: %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 %[[ELEM0]], … 26 …ide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32({{.}}, <4 x i1> %active.lane.mask 27 …de.masked.load1 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32({{.}}, <4 x i1> %active.lane.mask 29 ; PREDFLAG: call void @llvm.masked.store.v4i32.p0v4i32({{.}}, <4 x i1> %active.lane.mask 59 ; PREDFLAG: %[[ALM1:active.lane.mask.]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %… 60 ; PREDFLAG: %[[ALM2:active.lane.mask.]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %… 61 ; PREDFLAG: %[[ALM3:active.lane.mask.]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %… 62 ; PREDFLAG: %[[ALM4:active.lane.mask.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %…
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A D	mve-vmaxnma-tailpred.ll	35 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n) 38 …float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %1, i32 4, <4 x i1> %active.lane.mask, <4 x fl… 46 …llvm.masked.store.v4f32.p0v4f32(<4 x float> %5, <4 x float>* %7, i32 4, <4 x i1> %active.lane.mask) 85 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n) 97 …llvm.masked.store.v4f32.p0v4f32(<4 x float> %6, <4 x float>* %8, i32 4, <4 x i1> %active.lane.mask) 138 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %n) 149 …call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %5, <8 x half>* %7, i32 2, <8 x i1> %active.… 188 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %n) 200 …call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %6, <8 x half>* %8, i32 2, <8 x i1> %active.… 209 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) [all …]
H A D	mve-gather-scatter-tailpred.ll	44 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n) 58 %9 = select <4 x i1> %active.lane.mask, <4 x i32> %7, <4 x i32> %vec.phi 113 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n) 121 …call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %6, <4 x i32> %5, i32 4, <4 x i1> %active.… 128 %9 = select <4 x i1> %active.lane.mask, <4 x i32> %7, <4 x i32> %vec.phi 183 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n) 190 …call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %6, <4 x i32> %5, i32 4, <4 x i1> %active.… 197 %9 = select <4 x i1> %active.lane.mask, <4 x i32> %7, <4 x i32> %vec.phi 302 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N) 335 …call void @llvm.masked.scatter.v4i8.v4p0i8(<4 x i8> %l15, <4 x i8*> %l2, i32 1, <4 x i1> %active.l… [all …]
H A D	mve-zext-masked-load.ll	13 %active.lane.mask = icmp slt <4 x i16> %a, zeroinitializer 14 … i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %pSrc, i32 2, <4 x i1> %active.lane.mask, <4 x i1… 28 %active.lane.mask = icmp slt <8 x i8> %a, zeroinitializer 29 …<8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %pSrc, i32 1, <8 x i1> %active.lane.mask, <8 x i8… 44 %active.lane.mask = icmp slt <4 x i8> %a, zeroinitializer 45 …<4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %pSrc, i32 1, <4 x i1> %active.lane.mask, <4 x i8… 89 %active.lane.mask = icmp slt <4 x i32> %a, zeroinitializer 90 … i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %pSrc, i32 4, <4 x i1> %active.lane.mask, <4 x i3…
H A D	mve-sext-masked-load.ll	14 %active.lane.mask = icmp slt <4 x i16> %a, zeroinitializer 15 … i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %pSrc, i32 2, <4 x i1> %active.lane.mask, <4 x i1… 29 %active.lane.mask = icmp slt <8 x i8> %a, zeroinitializer 30 …<8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %pSrc, i32 1, <8 x i1> %active.lane.mask, <8 x i8… 45 %active.lane.mask = icmp slt <4 x i8> %a, zeroinitializer 46 …<4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %pSrc, i32 1, <4 x i1> %active.lane.mask, <4 x i8… 90 %active.lane.mask = icmp slt <4 x i32> %a, zeroinitializer 91 … i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %pSrc, i32 4, <4 x i1> %active.lane.mask, <4 x i3…
/llvm-project-15.0.7/openmp/runtime/src/
H A D	kmp_dispatch_hier.h	344 KMP_DEBUG_ASSERT(active > 0); in reset_shared_barrier() 345 if (active == 1) in reset_shared_barrier() 348 if (active >= 2 && active <= 8) { in reset_shared_barrier() 356 KMP_DEBUG_ASSERT(active > 0); in reset_private_barrier() 357 if (active == 1) in reset_private_barrier() 359 if (active >= 2 && active <= 8) { in reset_private_barrier() 367 KMP_DEBUG_ASSERT(active > 0); in barrier() 369 if (active == 1) { in barrier() 373 if (active >= 2 && active <= 8) { in barrier() 695 layers[i][j].active = 0; in allocate_hier() [all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A D	pr47299.ll	4 declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64, i64) 5 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64, i64) 6 declare <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64, i64) 7 declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64, i64) 8 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32) 9 declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i32(i32, i32) 52 %2 = call <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64 0, i64 %0) 66 %2 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 0, i64 %0) 83 %2 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 0, i64 %0) 108 %2 = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 0, i64 %0) [all …]
/llvm-project-15.0.7/clang/docs/
H A D	ItaniumMangleAbiTags.rst	30 All tags that are "active" on an <unqualified-name> are emitted after the 52 A namespace does not have any active tags. For types (class / struct / union / 53 enum), the explicit tags are the active tags. 55 For variables and functions, the active tags are the explicit tags plus any 61 active-tags := explicit-tags + derived-tags 99 For <local-name>s all active tags used in the local part (<function- 100 encoding>) are available, but not implicit tags which were not active. 106 std::__cxx11::basic_string<...>) will use 'cxx11' as an active tag, as it is
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A D	active_lane_mask.ll	23 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 0, i64 %tc) 87 %mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 %index, i64 %tc) 99 %mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 %index, i64 %tc) 118 %mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 %index, i64 %tc) 153 %mask = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 %index, i64 %tc) 225 declare <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64, i64) 226 declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64, i64) 227 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64, i64) 228 declare <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64, i64) 229 declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64, i64) [all …]
/llvm-project-15.0.7/libcxx/test/std/strings/basic.string/string.cons/
H A D	copy_alloc.pass.cpp	`22 bool active; member 24 TEST_CONSTEXPR alloc_imp() : active(true) {} in alloc_imp() 29 if (active) in allocate() 37 void activate () { active = true; } in activate() 38 void deactivate() { active = false; } in deactivate()`

12 3 4 5 6 7 8 9

TaskScheduler
dpdk
expo
f-stack
freebsd-12.1
freebsd-13.1
freebsd-14.2
iperf
leveldb-1.20
libedit-20250104-3.1
libev
libevent-2.1.12
libpciaccess
libtiff-4.0.7
lighttpd1.4
linux-6.15
llvm-project-15.0.7
mOS-networking-stack
memcached-1.4.29
memcached-1.6.32
oneTBB
pciutils
potrace-1.14
redis-3.2.3
rocksdb-6.9
rust-libc-0.2.174
sqlite-3.40.0
tonic
vim-8.2.3635
wasmtime-44.0.1
webrtc
xiu
xnu-11215