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Searched refs:abs32 (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A Dconstpool.ll1 …%s -mtriple=sparc -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s
2 …%s -mtriple=sparcv9 -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s
13 ; abs32: floatCP
14 ; abs32: sethi %hi(.LCPI0_0), %[[R:[gilo][0-7]]]
15 ; abs32: retl
16 ; abs32: ld [%[[R]]+%lo(.LCPI0_0)], %f
H A Dglobals.ll1 …%s -mtriple=sparc -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s
2 …%s -mtriple=sparcv9 -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s
15 ; abs32: loadG
16 ; abs32: sethi %hi(G), %[[R:[gilo][0-7]]]
17 ; abs32: retl
18 ; abs32: ldub [%[[R]]+%lo(G)], %o0
H A Dfunc-addr.ll1 …%s -mtriple=sparc -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s
2 …%s -mtriple=sparcv9 -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s
21 ; abs32-LABEL: test
22 ; abs32: sethi %hi(func1), %i0
23 ; abs32: add %i0, %lo(func1), %i1
24 ; abs32: call %i0+%lo(func1)
H A Dblockaddr.ll1 …%s -mtriple=sparc -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s
2 …%s -mtriple=sparcv9 -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s
18 ; abs32-LABEL: func_block_addr:
19 ; abs32: sethi %hi([[BLK:.+]]), [[R:%[gilo][0-7]]]
20 ; abs32: call dummy
21 ; abs32: add [[R]], %lo([[BLK]]), %o0
22 ; abs32: jmp %o0
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dlds-relocs.ll35 ; GCN: v_mov_b32_e32 v1, lds.external@abs32@lo ; encoding: [0xff,0x02,0x02,0x7e,A,A,A,A]
36 ; GCN-NEXT: ; fixup A - offset: 4, value: lds.external@abs32@lo, kind: FK_Data_4{{$}}
38 ; GCN: s_add_i32 s0, s0, lds.defined@abs32@lo ; encoding: [0x00,0xff,0x00,0x81,A,A,A,A]
39 ; GCN-NEXT: ; fixup A - offset: 4, value: lds.defined@abs32@lo, kind: FK_Data_4{{$}}
H A Dllvm.amdgcn.groupstaticsize.ll15 ; NOHSA: v_mov_b32_e32 v{{[0-9]+}}, llvm.amdgcn.groupstaticsize@abs32@lo
30 ; NOHSA: v_mov_b32_e32 v{{[0-9]+}}, llvm.amdgcn.groupstaticsize@abs32@lo
59 ; NOHSA: v_mov_b32_e32 v{{[0-9]+}}, llvm.amdgcn.groupstaticsize@abs32@lo
H A Dvopd-combine.mir511 ; SCHED-NEXT: $vgpr2 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, implicit $exec
513 ; SCHED-NEXT: $vgpr4 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, implicit $exec
514 ; SCHED-NEXT: $vgpr5 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, implicit $exec
519 … = V_DUAL_MOV_B32_e32_X_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, target-flags(amdgpu-abs32-…
523 $vgpr2 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, implicit $exec
526 $vgpr4 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, implicit $exec
527 $vgpr5 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, implicit $exec
536 ; SCHED: $vgpr0 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, implicit $exec
539 ; PAIR: $vgpr0 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, implicit $exec
541 $vgpr0 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, implicit $exec
[all …]
H A Damdgpu-reloc-const.ll8 ; GCN: v_mov_b32_{{.*}} v[[relocreg:[0-9]+]], doff_0_0_b@abs32@lo
H A Dlds-zero-initializer.ll23 …; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, im…
H A Damdgcn-load-offset-from-reg.ll10 ; GCN: %[[OFFSET:[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @DescriptorBuffer
H A Dds_write2.ll178 ; TODO: GFX9 has v_mov_b32_e32 v2, lds@abs32@lo
/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Delf-lds.s8 s_mov_b32 s0, lds0@abs32@lo
12 s_mov_b32 s0, lds4@abs32@lo
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/AMDGPU/
H A Dtarget-flags.mir30 %2:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @foo
31 %3:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @foo
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dinst-select-amdgcn.reloc.constant.mir24 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @arst
42 …; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @arst, imp…
H A Dinst-select-amdgcn.groupstaticsize.mir21 …; MESA: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @llvm.amd…
42 …; MESA: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @llvm.amdgcn.grou…
H A Dlds-relocs.ll8 ; GCN: s_add_u32 s0, lds.defined@abs32@lo, s0 ; encoding: [0xff,0x00,0x00,0x80,A,A,A,A]
H A Dlds-zero-initializer.ll17 ; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @lds
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dneg-abs.ll74 define i32 @abs32(i32 %x) {
75 ; CHECK-LABEL: abs32:
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dabs.ll140 define i32 @abs32(i32 %x) {
141 ; CHECKT1-LABEL: abs32:
148 ; CHECKT2-LABEL: abs32:
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Diabs.ll225 define i32 @abs32(i32 %x) {
226 ; RV32I-LABEL: abs32:
233 ; RV32ZBB-LABEL: abs32:
239 ; RV32ZBT-LABEL: abs32:
246 ; RV64I-LABEL: abs32:
253 ; RV64ZBB-LABEL: abs32:
260 ; RV64ZBT-LABEL: abs32:
/llvm-project-15.0.7/llvm/test/MC/CSKY/
H A Dbasic.s305 # CHECK-ASM-AND-OBJ: abs32 a3, l0
307 abs32 a3, l0 label
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td601 // revh32, abs32, ff0.32, ff1.32, bgenr32
H A DCSKYInstrInfo.td873 def ABS32 : R_XZ<0x0, 0x10, "abs32">;