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/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dabs_intrinsic.ll60 %abs = call i32 @llvm.abs.i32(i32 %zext, i1 false)
82 %abs = call i32 @llvm.abs.i32(i32 %and, i1 true)
108 %abs = call i32 @llvm.abs.i32(i32 %x, i1 true)
116 %abs = call i32 @llvm.abs.i32(i32 %x, i1 true)
137 %abs = call i32 @llvm.abs.i32(i32 %x, i1 false)
178 %abs = call i32 @llvm.abs.i32(i32 %or, i1 false)
198 %abs = call i32 @llvm.abs.i32(i32 %x, i1 true)
207 %abs = call i8 @llvm.abs.i8(i8 %x, i1 false)
217 %abs = call i32 @llvm.abs.i32(i32 %x, i1 false)
233 %abs = call i32 @llvm.abs.i32(i32 %x, i1 false)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dmath-intrins-sm86-ptx72.ll41 ; CHECK: min.xorsign.abs.f16
49 ; CHECK: min.ftz.xorsign.abs.f16
73 ; CHECK: min.xorsign.abs.f16x2
105 ; CHECK: min.xorsign.abs.bf16
137 ; CHECK: min.xorsign.abs.f
145 ; CHECK: min.ftz.xorsign.abs.f
153 ; CHECK: min.NaN.xorsign.abs.f
169 ; CHECK: max.xorsign.abs.f16
201 ; CHECK: max.xorsign.abs.f16x2
233 ; CHECK: max.xorsign.abs.bf16
[all …]
H A Didioms.ll10 ; CHECK: abs.s16
12 %abs.cond = icmp sge i16 %a, 0
13 %abs = select i1 %abs.cond, i16 %a, i16 %neg
14 ret i16 %abs
19 ; CHECK: abs.s32
21 %abs.cond = icmp sge i32 %a, 0
22 %abs = select i1 %abs.cond, i32 %a, i32 %neg
23 ret i32 %abs
28 ; CHECK: abs.s64
31 %abs = select i1 %abs.cond, i64 %a, i64 %neg
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/ARM/
H A Dmve-abs.ll7 declare i64 @llvm.abs.i64(i64, i1)
8 declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1)
9 declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)
10 declare <8 x i64> @llvm.abs.v8i64(<8 x i64>, i1)
12 declare i32 @llvm.abs.i32(i32, i1)
18 declare i16 @llvm.abs.i16(i16, i1)
25 declare i8 @llvm.abs.i8(i8, i1)
26 declare <2 x i8> @llvm.abs.v2i8(<2 x i8>, i1)
33 define i32 @abs(i32 %arg) {
34 ; MVE-RECIP-LABEL: 'abs'
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/
H A Dabs.ll5 declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1)
6 declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)
7 declare <8 x i64> @llvm.abs.v8i64(<8 x i64>, i1)
9 declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1)
10 declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
20 declare <2 x i8> @llvm.abs.v2i8(<2 x i8>, i1)
21 declare <4 x i8> @llvm.abs.v4i8(<4 x i8>, i1)
22 declare <8 x i8> @llvm.abs.v8i8(<8 x i8>, i1)
27 define i32 @abs(i32 %arg) {
28 ; RECIP-LABEL: 'abs'
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dneg-abs.ll19 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
31 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %0, i1 true)
32 %neg.abs = sub <2 x i64> zeroinitializer, %abs
33 ret <2 x i64> %neg.abs
43 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %0, i1 true)
44 %neg.abs = sub <4 x i32> zeroinitializer, %abs
45 ret <4 x i32> %neg.abs
55 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %0, i1 true)
56 %neg.abs = sub <8 x i16> zeroinitializer, %abs
67 %abs = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %0, i1 true)
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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dneg-abs.ll13 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
26 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
40 %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
57 %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
70 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
71 ret i64 %abs
80 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
81 ret i32 %abs
91 %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
92 ret i16 %abs
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H A Dneon-abd.ll18 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)
31 %abs = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %sub, i1 true)
44 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)
61 %abs = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %sub, i1 true)
73 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 true)
86 %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)
98 %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)
115 %abs = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %sub, i1 true)
127 %abs = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %sub, i1 true)
140 %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)
[all …]
H A Dsve-abd.ll19 %abs = call <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16> %sub, i1 true)
35 %abs = call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> %sub, i1 true)
36 ret <vscale x 16 x i8> %abs
48 %abs = call <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32> %sub, i1 true)
64 %abs = call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> %sub, i1 true)
65 ret <vscale x 8 x i16> %abs
77 %abs = call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> %sub, i1 true)
93 %abs = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %sub, i1 true)
122 %abs = call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %sub, i1 true)
155 %abs = call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> %sub, i1 true)
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/X86/
H A Dabs.ll12 ; abs(X, not_posion)
58 %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 0)
108 %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 0)
172 %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 0)
236 %I8 = call i8 @llvm.abs.i8(i8 %a8, i1 0)
244 ; abs(X, posion)
468 %I8 = call i8 @llvm.abs.i8(i8 %a8, i1 -1)
475 declare i64 @llvm.abs.i64(i64, i1)
476 declare i32 @llvm.abs.i32(i32, i1)
477 declare i16 @llvm.abs.i16(i16, i1)
[all …]
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dwarn-absolute-value.cpp5 int abs(int);
21 int abs(int);
26 float abs(float);
27 double abs(double);
31 double abs(T);
36 (void)std::abs(x); in test_int()
38 (void)abs(x); in test_int()
167 (void)abs(x); in test_long_long()
243 (void)abs(x); in test_float()
307 (void)abs(x); in test_double()
[all …]
H A Dwarn-absolute-value-header.cpp5 int abs(int);
10 int abs(int);
11 float abs(float);
16 (void)abs(d); in test()
29 (void)abs(ll); in test()
41 (void)abs(i); in test()
49 (void)abs(f); in test()
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dabs-intrinsic.ll18 %abs = call i32 @llvm.abs.i32(i32 %and, i1 false)
45 %abs = call i32 @llvm.abs.i32(i32 %and, i1 false)
73 %abs = call i32 @llvm.abs.i32(i32 %ext, i1 false)
118 %abs = call i32 @llvm.abs.i32(i32 %sel, i1 true)
205 %abs = call i32 @llvm.abs.i32(i32 %and, i1 true)
227 %abs = call i32 @llvm.abs.i32(i32 %x, i1 true)
242 %abs = call i32 @llvm.abs.i32(i32 %x, i1 false)
262 %abs = call i8 @llvm.abs.i8(i8 %x, i1 true)
271 %abs = call i8 @llvm.abs.i8(i8 %x, i1 true)
281 %abs = call i8 @llvm.abs.i8(i8 %x, i1 false)
[all …]
H A Dabs-1.ll50 ret i8 %abs
89 ret i8 %abs
100 ret i8 %abs
113 ret i32 %abs
126 ret i32 %abs
151 ret i32 %abs
180 ret i32 %abs
194 ret i8 %abs
236 ret i8 %abs
248 ret i8 %abs
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/SVE/
H A Dabs.s12 abs z0.b, p0/m, z0.b label
18 abs z0.h, p0/m, z0.h label
24 abs z0.s, p0/m, z0.s label
30 abs z0.d, p0/m, z0.d label
36 abs z31.b, p7/m, z31.b label
42 abs z31.h, p7/m, z31.h label
48 abs z31.s, p7/m, z31.s label
54 abs z31.d, p7/m, z31.d label
70 abs z4.d, p7/m, z31.d label
82 abs z4.d, p7/m, z31.d label
/llvm-project-15.0.7/llvm/test/tools/llvm-cov/gcov/
H A Drelative-only.test4 RUN: cp %S/Inputs/abs-path.gcno %S/Inputs/abs-path.gcda .
6 RUN: llvm-cov gcov abs-path.gcda | FileCheck %s
7 RUN: rm abs-path.c.gcov a.h.gcov
8 CHECK: File '/tmp/c/abs-path.c'
12 RUN: llvm-cov gcov -r abs-path.gcda 2>&1 | count 0
13 RUN: llvm-cov gcov -r -s /t abs-path.gcda 2>&1 | count 0
14 RUN: not ls abs-path.c.gcov 2> /dev/null
18 RUN: FileCheck %s --check-prefix=STRIP1_C < abs-path.c.gcov
24 STRIP1:File 'c/abs-path.c'
26 STRIP1-NEXT:Creating 'abs-path.c.gcov'
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dnan-fp-attr.ll19 ; Test that the instruction selection for the case of `abs.s` and `abs.d`
21 ; mode MIPS treats abs.s and abs.d as arithmetic fp instructions triggering
35 ; MIPS32R1-NEXT: abs.d $f0, $f12
40 ; MIPS32R2-NEXT: abs.d $f0, $f12
50 ; MIPS32R6-NEXT: abs.d $f0, $f12
80 ; MM-NEXT: abs.d $f0, $f12
89 ; MMR6-NEXT: abs.d $f0, $f12
176 ; MMR6-NEXT: abs.d $f0, $f12
232 ; MM-NEXT: abs.s $f0, $f12
241 ; MMR6-NEXT: abs.s $f0, $f12
[all …]
/llvm-project-15.0.7/libcxx/test/std/depr/depr.c.headers/
H A Dstdlib_h.pass.cpp17 #ifdef abs
18 #error abs is defined
61 template <class T, class = decltype(::abs(std::declval<T>()))>
72 static_assert((std::is_same<decltype(abs((float)0)), float>::value), ""); in test_abs()
76 static_assert((std::is_same<decltype(abs((int)0)), int>::value), ""); in test_abs()
77 static_assert((std::is_same<decltype(abs((long)0)), long>::value), ""); in test_abs()
84 static_assert((std::is_same<decltype(abs((signed char)0)), int>::value), in test_abs()
86 static_assert((std::is_same<decltype(abs((short)0)), int>::value), in test_abs()
90 static_assert((std::is_same<decltype(abs((char)0)), int>::value), in test_abs()
100 assert(abs(-1.) == 1); in test_abs()
[all …]
/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dfma-mix.s21 v_fma_mix_f32 v0, abs(v1), v2, v3
25 v_fma_mix_f32 v0, v1, abs(v2), v3
29 v_fma_mix_f32 v0, v1, v2, abs(v3)
45 v_fma_mix_f32 v0, -abs(v1), v2, v3
49 v_fma_mix_f32 v0, v1, -abs(v2), v3
53 v_fma_mix_f32 v0, v1, v2, -abs(v3)
57 v_fma_mixlo_f16 v0, abs(v1), -v2, abs(v3)
61 v_fma_mixhi_f16 v0, -v1, abs(v2), -abs(v3)
H A Dmad-mix.s21 v_mad_mix_f32 v0, abs(v1), v2, v3
25 v_mad_mix_f32 v0, v1, abs(v2), v3
29 v_mad_mix_f32 v0, v1, v2, abs(v3)
45 v_mad_mix_f32 v0, -abs(v1), v2, v3
49 v_mad_mix_f32 v0, v1, -abs(v2), v3
53 v_mad_mix_f32 v0, v1, v2, -abs(v3)
57 v_mad_mixlo_f16 v0, abs(v1), -v2, abs(v3)
61 v_mad_mixhi_f16 v0, -v1, abs(v2), -abs(v3)
/llvm-project-15.0.7/libcxx/test/std/numerics/rand/rand.dist/rand.dist.uni/rand.dist.uni.real/
H A Deval.pass.cpp73 assert(std::abs(skew - x_skew) < 0.01); in main()
113 assert(std::abs(skew - x_skew) < 0.01); in main()
153 assert(std::abs(skew - x_skew) < 0.01); in main()
193 assert(std::abs(skew - x_skew) < 0.01); in main()
233 assert(std::abs(skew - x_skew) < 0.02); in main()
273 assert(std::abs(skew - x_skew) < 0.01); in main()
313 assert(std::abs(skew - x_skew) < 0.01); in main()
353 assert(std::abs(skew - x_skew) < 0.01); in main()
393 assert(std::abs(skew - x_skew) < 0.01); in main()
431 assert(std::abs(mean - x_mean) < 0.01); in main()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dabs.ll27 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
47 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
69 %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
112 %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
136 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
137 ret i64 %abs
154 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
155 ret i32 %abs
173 %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
174 ret i16 %abs
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/CorrelatedValuePropagation/
H A Dabs.ll5 declare i8 @llvm.abs(i8, i1)
14 %r = call i8 @llvm.abs(i8 %x, i1 0)
22 %r = call i8 @llvm.abs(i8 %x, i1 1)
38 %r = call i8 @llvm.abs(i8 %x, i1 0)
51 %r = call i8 @llvm.abs(i8 %x, i1 1)
64 %r = call i8 @llvm.abs(i8 %x, i1 0)
76 %r = call i8 @llvm.abs(i8 %x, i1 1)
89 %r = call i8 @llvm.abs(i8 %x, i1 0)
101 %r = call i8 @llvm.abs(i8 %x, i1 1)
116 %r = call i8 @llvm.abs(i8 %x, i1 0)
[all …]
/llvm-project-15.0.7/libcxx/test/std/numerics/rand/rand.dist/rand.dist.samp/rand.dist.samp.pconst/
H A Deval.pass.cpp92 assert(std::abs(skew - x_skew) < 0.01); in test1()
155 assert(std::abs(skew - x_skew) < 0.01); in test2()
218 assert(std::abs(skew - x_skew) < 0.01); in test3()
281 assert(std::abs(skew - x_skew) < 0.01); in test4()
344 assert(std::abs(skew - x_skew) < 0.01); in test5()
407 assert(std::abs(skew - x_skew) < 0.01); in test6()
470 assert(std::abs(skew - x_skew) < 0.01); in test7()
533 assert(std::abs(skew - x_skew) < 0.01); in test8()
596 assert(std::abs(skew - x_skew) < 0.01); in test9()
659 assert(std::abs(skew - x_skew) < 0.01); in test10()
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/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dint-neg-02.ll13 %res = sub i32 0, %abs
25 %res = sub i32 0, %abs
37 %res = sub i32 0, %abs
49 %res = sub i32 0, %abs
62 %res = sub i64 0, %abs
77 %res = sub i64 0, %abs
89 %res = sub i64 0, %abs
103 %res = sub i64 0, %abs
117 %res = sub i64 0, %abs
131 %res = sub i64 0, %abs
[all …]

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