Home
last modified time | relevance | path

Searched refs:a6 (Results 1 – 25 of 406) sorted by relevance

12345678910>>...17

/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Durem-vector-lkk.ll65 ; RV32IM-NEXT: srli a6, a6, 1
73 ; RV32IM-NEXT: addi a6, a6, 529
151 ; RV64IM-NEXT: srli a6, a6, 1
243 ; RV32IM-NEXT: add a6, a7, a6
244 ; RV32IM-NEXT: srli a6, a6, 6
246 ; RV32IM-NEXT: mul a6, a6, a7
251 ; RV32IM-NEXT: add a6, t0, a6
252 ; RV32IM-NEXT: srli a6, a6, 6
253 ; RV32IM-NEXT: mul a6, a6, a7
258 ; RV32IM-NEXT: add a6, t0, a6
[all …]
H A Dsrem-vector-lkk.ll251 ; RV32IM-NEXT: add a6, a6, a4
253 ; RV32IM-NEXT: srli a6, a6, 6
254 ; RV32IM-NEXT: add a6, a6, a7
256 ; RV32IM-NEXT: mul a6, a6, a7
259 ; RV32IM-NEXT: add a6, a6, a1
261 ; RV32IM-NEXT: srli a6, a6, 6
262 ; RV32IM-NEXT: add a6, a6, t0
263 ; RV32IM-NEXT: mul a6, a6, a7
266 ; RV32IM-NEXT: add a6, a6, a3
268 ; RV32IM-NEXT: srli a6, a6, 6
[all …]
H A Drotl-rotr.ll99 ; RV32I-NEXT: neg a6, a2
110 ; RV32I-NEXT: srl a6, a0, a6
149 ; RV32ZBB-NEXT: neg a6, a2
160 ; RV32ZBB-NEXT: srl a6, a0, a6
203 ; RV32I-NEXT: neg a6, a2
214 ; RV32I-NEXT: sll a6, a1, a6
264 ; RV32ZBB-NEXT: sll a6, a1, a6
1062 ; RV32I-NEXT: xori a6, a6, 31
1115 ; RV32ZBB-NEXT: xori a6, a6, 31
1205 ; RV32I-NEXT: or a6, a6, t0
[all …]
H A Daddcarry.ll15 ; RISCV32-NEXT: add a6, a5, a4
17 ; RISCV32-NEXT: add a4, a6, a4
18 ; RISCV32-NEXT: sltu a7, a4, a6
19 ; RISCV32-NEXT: sltu a5, a6, a5
20 ; RISCV32-NEXT: mulhu a6, a0, a3
21 ; RISCV32-NEXT: add a5, a6, a5
22 ; RISCV32-NEXT: mulhu a6, a1, a2
23 ; RISCV32-NEXT: add a5, a5, a6
25 ; RISCV32-NEXT: mul a6, a1, a3
26 ; RISCV32-NEXT: add a5, a5, a6
H A Dshifts.ll151 ; RV32I-NEXT: neg a6, a2
155 ; RV32I-NEXT: sll t0, a5, a6
161 ; RV32I-NEXT: sll a6, a4, a6
166 ; RV32I-NEXT: or t2, a6, a7
197 ; RV32I-NEXT: srl t5, t5, a6
228 ; RV32I-NEXT: srl a5, a4, a6
287 ; RV32I-NEXT: neg a6, a2
297 ; RV32I-NEXT: sll a6, a4, a6
302 ; RV32I-NEXT: or t4, a6, a7
424 ; RV32I-NEXT: neg a6, a2
[all …]
H A Dxaluo.ll999 ; RV32-NEXT: sltu a6, a5, a6
1001 ; RV32-NEXT: add a6, a7, a6
1018 ; RV32-NEXT: sltu a6, a7, a6
1020 ; RV32-NEXT: add a6, a7, a6
1021 ; RV32-NEXT: add a6, a6, t0
1149 ; RV32-NEXT: add a6, a5, a6
1371 ; RV32-NEXT: sltu a6, a5, a6
2428 ; RV32-NEXT: add a6, a7, a6
2429 ; RV32-NEXT: add a6, a5, a6
2788 ; RV32-NEXT: snez a6, a6
[all …]
H A Drv32zbp.ll47 ; RV32I-NEXT: addi a6, a6, 1365
110 ; RV32I-NEXT: addi a6, a6, 819
189 ; RV32I-NEXT: addi a6, a6, 1365
205 ; RV32I-NEXT: addi a6, a6, 819
274 ; RV32I-NEXT: addi a6, a6, -241
353 ; RV32I-NEXT: addi a6, a6, 1365
369 ; RV32I-NEXT: addi a6, a6, -241
454 ; RV32I-NEXT: addi a6, a6, 819
1091 ; RV32I-NEXT: and a6, a6, a7
1223 ; RV32I-NEXT: and a6, a6, a7
[all …]
H A Dloop-strength-reduce-add-cheaper-than-mul.ll66 ; RV64-NEXT: slli a6, a5, 32
67 ; RV64-NEXT: srli a6, a6, 32
68 ; RV64-NEXT: add a6, a3, a6
69 ; RV64-NEXT: sb zero, 0(a6)
H A Diabs.ll442 ; RV32I-NEXT: mv a6, a5
445 ; RV32I-NEXT: snez a6, a2
473 ; RV32ZBB-NEXT: mv a6, a5
476 ; RV32ZBB-NEXT: snez a6, a2
506 ; RV32ZBT-NEXT: cmov a6, a3, a6, a5
515 ; RV32ZBT-NEXT: sub a6, a7, a6
572 ; RV32I-NEXT: mv a6, a5
575 ; RV32I-NEXT: snez a6, a2
603 ; RV32ZBB-NEXT: mv a6, a5
636 ; RV32ZBT-NEXT: cmov a6, a3, a6, a5
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-profgen/Inputs/
H A Dprofile-density-cs.raw.prof84 7a6-7a6:1273
88 7a6->650:817
89 7a6->710:489
144 7a6-7a6:331
150 7a6->650:248
151 7a6->710:103
H A Dcold-profile-trimming.raw.prof22 400790-4007a6:12
47 4007a6->400650:7
48 4007a6->400710:5
/llvm-project-15.0.7/llvm/test/CodeGen/M68k/Alloc/
H A Ddyn_alloca_aligned.ll7 ; CHECK-NEXT: move.l %a6, -(%sp)
9 ; CHECK-NEXT: .cfi_offset %a6, -8
10 ; CHECK-NEXT: move.l %sp, %a6
11 ; CHECK-NEXT: .cfi_def_cfa_register %a6
18 ; CHECK-NEXT: move.l (8,%a6), %d1
26 ; CHECK-NEXT: move.l %a6, %sp
27 ; CHECK-NEXT: move.l (%sp)+, %a6
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/ir-instruction/
H A Dmul.ll169 ; LA32-NEXT: add.w $a5, $a6, $a5
170 ; LA32-NEXT: mul.w $a6, $a0, $a3
171 ; LA32-NEXT: add.w $a4, $a6, $a4
172 ; LA32-NEXT: sltu $a4, $a4, $a6
174 ; LA32-NEXT: add.w $a4, $a6, $a4
178 ; LA32-NEXT: add.w $a5, $a6, $a5
179 ; LA32-NEXT: mul.w $a6, $a1, $a3
180 ; LA32-NEXT: add.w $a4, $a6, $a4
181 ; LA32-NEXT: sltu $a6, $a4, $a6
182 ; LA32-NEXT: add.w $a5, $a5, $a6
[all …]
/llvm-project-15.0.7/clang/test/Lexer/
H A Dsize_t-literal.cpp25 auto a6 = 1UZ; in ValidSuffix() local
43 auto a6 = 0x1UZ; in ValidSuffix() local
61 auto a6 = 0b1UZ; in ValidSuffix() local
79 auto a6 = 01UZ; in ValidSuffix() local
100 auto a6 = 1Zl; // expected-error {{invalid suffix}} in InvalidSuffix() local
122 auto a6 = 1Zll; // expected-error {{invalid suffix}} in InvalidSuffix() local
143 auto a6 = 0.1UZ; // expected-error {{invalid suffix}} in InvalidSuffix() local
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drv32a-valid.s50 # CHECK-ASM-AND-OBJ: amoor.w a4, a5, (a6)
52 amoor.w a4, a5, (a6)
53 # CHECK-ASM-AND-OBJ: amomin.w a5, a6, (a7)
55 amomin.w a5, a6, (a7)
78 # CHECK-ASM-AND-OBJ: amoor.w.aq a4, a5, (a6)
80 amoor.w.aq a4, a5, (a6)
83 amomin.w.aq a5, a6, (a7)
108 amoor.w.rl a4, a5, (a6)
111 amomin.w.rl a5, a6, (a7)
136 amoor.w.aqrl a4, a5, (a6)
[all …]
H A Drvzdinx-aliases-valid.s26 # CHECK-INST: fmadd.d a0, a2, a4, a6, dyn
27 # CHECK-ALIAS: fmadd.d a0, a2, a4, a6
29 # CHECK-INST: fmsub.d a0, a2, a4, a6, dyn
30 # CHECK-ALIAS: fmsub.d a0, a2, a4, a6
32 # CHECK-INST: fnmsub.d a0, a2, a4, a6, dyn
33 # CHECK-ALIAS: fnmsub.d a0, a2, a4, a6
35 # CHECK-INST: fnmadd.d a0, a2, a4, a6, dyn
36 # CHECK-ALIAS: fnmadd.d a0, a2, a4, a6
H A Drv64a-valid.s60 # CHECK-ASM-AND-OBJ: amoor.d a4, a5, (a6)
63 amoor.d a4, a5, (a6)
64 # CHECK-ASM-AND-OBJ: amomin.d a5, a6, (a7)
67 amomin.d a5, a6, (a7)
98 # CHECK-ASM-AND-OBJ: amoor.d.aq a4, a5, (a6)
101 amoor.d.aq a4, a5, (a6)
105 amomin.d.aq a5, a6, (a7)
138 amoor.d.rl a4, a5, (a6)
142 amomin.d.rl a5, a6, (a7)
175 amoor.d.aqrl a4, a5, (a6)
[all …]
H A Drv32zdinx-valid.s12 # CHECK-ASM-AND-OBJ: fmadd.d a0, a2, a4, a6, dyn
15 # CHECK-ASM-AND-OBJ: fmsub.d a0, a2, a4, a6, dyn
18 # CHECK-ASM-AND-OBJ: fnmsub.d a0, a2, a4, a6, dyn
21 # CHECK-ASM-AND-OBJ: fnmadd.d a0, a2, a4, a6, dyn
87 # CHECK-ASM-AND-OBJ: fmadd.d a0, a2, a4, a6, rne
90 # CHECK-ASM-AND-OBJ: fmsub.d a0, a2, a4, a6, rtz
93 # CHECK-ASM-AND-OBJ: fnmsub.d a0, a2, a4, a6, rdn
96 # CHECK-ASM-AND-OBJ: fnmadd.d a0, a2, a4, a6, rup
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dfixed-vector-trunc-vp.ll276 ; CHECK-NEXT: mv a5, a6
294 ; CHECK-NEXT: slli a6, a6, 4
295 ; CHECK-NEXT: add a6, sp, a6
296 ; CHECK-NEXT: addi a6, a6, 16
308 ; CHECK-NEXT: mul a6, a6, t0
309 ; CHECK-NEXT: add a6, sp, a6
310 ; CHECK-NEXT: addi a6, a6, 16
320 ; CHECK-NEXT: mv a6, a2
354 ; CHECK-NEXT: mul a6, a6, t1
355 ; CHECK-NEXT: add a6, sp, a6
[all …]
/llvm-project-15.0.7/polly/test/ScopInfo/
H A Dmultidim_many_references.ll315 %a6.tmp1 = add i64 %a6.cols, 1
316 %a6.tmp2 = mul i64 %a6.deps, %a6.tmp1
317 %a6.tmp3 = add i64 %a6.tmp2, 1
318 %a6.tmp4 = mul i64 %a6.cols, %a6.deps
319 %a6.idx.i = mul i64 %a6.tmp4, %indvar.i
320 %a6.tmp5 = add i64 %a6.tmp3, %a6.idx.i
321 %a6.idx.j = mul i64 %a6.deps, %indvar.j
322 %a6.tmp6 = add i64 %a6.tmp5, %a6.idx.j
323 %a6.idx.k = add i64 %a6.tmp6, %indvar.k
324 %a6.ptr = getelementptr float, float* %a6.data, i64 %a6.idx.k
[all …]
/llvm-project-15.0.7/llvm/test/MC/M68k/Arith/Classes/
H A DMxCMP_MI.s53 ; CHECK: cmpi.l #-1, (0,%a6,%a0)
55 cmpi.l #-1, (0,%a6,%a0)
72 ; CHECK: cmpi.l #-1, (0,%a6)
74 cmpi.l #-1, (0,%a6)
91 ; CHECK: cmpi.l #-1, (%a6)
93 cmpi.l #-1, (%a6)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-fast-isel-call.ll109 define zeroext i1 @call_arguments1(i1 %a1, i1 %a2, i1 %a3, i1 %a4, i1 %a5, i1 %a6, i1 %a7, i1 %a8) {
117 %3 = and i1 %a5, %a6
136 %a6s = sext i8 %a6 to i32
160 %a6s = sext i16 %a6 to i32
173 define i32 @call_arguments4(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8)…
181 %3 = add i32 %a5, %a6
189 define i64 @call_arguments5(i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i64 %a7, i64 %a8)…
197 %3 = add i64 %a5, %a6
213 %3 = fadd float %a5, %a6
229 %3 = fadd double %a5, %a6
[all …]
/llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Integer/
H A Dbit-shift.s24 # CHECK-ASM-AND-OBJ: sra.w $t0, $s5, $a6
26 sra.w $t0, $s5, $a6
36 # CHECK-ASM-AND-OBJ: srli.w $a6, $t2, 30
38 srli.w $a6, $t2, 30
71 # CHECK64-ASM-AND-OBJ: slli.d $a6, $s8, 39
73 slli.d $a6, $s8, 39
H A Dcrc.s12 # CHECK-ASM-AND-OBJ: crc.w.h.w $s8, $a6, $t6
14 crc.w.h.w $s8, $a6, $t6
16 # CHECK-ASM-AND-OBJ: crc.w.w.w $s5, $a2, $a6
18 crc.w.w.w $s5, $a2, $a6
/llvm-project-15.0.7/libcxx/benchmarks/
H A Dstringstream.bench.cpp15 int a1, a2, a3, a4, a5, a6, a7; in istream_numbers() local
26 >> a6 in istream_numbers()
28 q += (a1 + a2 + a3 + a4 + a5 + a6 + a7 + f1 + f2)/1000000; in istream_numbers()

12345678910>>...17