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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td1875 def _D : SVEPseudo2Instr<Ps # _D, 1>, sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>;
1918 SVEPseudo2Instr<Ps # _D, 1>, SVEInstr2Rev<NAME # _D, revname # _D, isReverseInstr>;
2098 SVEPseudo2Instr<Ps # _D, 1>, SVEInstr2Rev<NAME # _D, revname # _D, isReverseInstr>;
2138 SVEInstr2Rev<NAME # _D, revname # _D, isReverseInstr>;
2830 SVEPseudo2Instr<Ps # _D, 1>, SVEInstr2Rev<NAME # _D, revname # _D, isReverseInstr>;
2850 SVEPseudo2Instr<Ps # _D, 1>;
2888 SVEPseudo2Instr<Ps # _D, 1>, SVEInstr2Rev<NAME # _D, revname # _D, isReverseInstr>;
3455 SVEPseudo2Instr<Ps # _D, 1>, SVEInstr2Rev<NAME # _D, revname # _D, isReverseInstr>;
5463 def _D : SVEPseudo2Instr<Ps # _D, 1>,
5509 def _D : SVEPseudo2Instr<Ps # _D, 1>,
[all …]
H A DSMEInstrFormats.td384 def _D : sme_mem_ld_ss_inst<0b0, 0b11, mnemonic # "d",
522 def _D : sme_mem_st_ss_inst<0b0, 0b11, mnemonic # "d",
554 defm : sme_mem_st_ss_patterns<!cast<Instruction>(NAME # _D),
769 defm : sme_vector_to_tile_aliases<!cast<Instruction>(NAME # _D),
938 defm : sme_tile_to_vector_aliases<!cast<Instruction>(NAME # _D), ZPR64,
966 defm : sme_tile_to_vector_patterns<!cast<Instruction>(NAME # _D),
969 defm : sme_tile_to_vector_patterns<!cast<Instruction>(NAME # _D),
1108 def _D : sve2_clamp<asm, 0b11, U, ZPR64>;
1154 def _D : sve2_int_perm_sel_p<asm, PPR64, sme_elm_idx0_1> {
1172 (!cast<Instruction>(NAME # _D) $Pn, $Pm, $idx, 0)>;
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H A DAArch64SchedNeoverseN2.td1710 def : InstRW<[N2Write_4cyc_1V0], (instregex "^[SU]DOT_ZZZI?_D$")>;
1755 def : InstRW<[N2Write_8cyc_2M0_2V0], (instregex "^INDEX_(IR|RI|RR)_D$")>;
1783 def : InstRW<[N2Write_5cyc_2V0], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D$",
1784 "^[SU]MULH_(ZPmZ|ZZZ)_D$")>;
1826 def : InstRW<[N2Write_5cyc_2V0], (instregex "^SQRDML[AS]H_ZZZI?_D$",
1834 def : InstRW<[N2Write_5cyc_2V0], (instregex "^SQRDMULH_ZZZI?_D$")>;
2242 def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^SST1[BHW]_D$",
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrFormatsF1.td84 def _D : F_MOV<1, sop, op, "d", sFPR64Op>;
90 def _D : F_XZ<1, sop, op, "d", opnode, sFPR64Op>;
113 def _D : F_XYZ<1, sop, op, "d", opnode, sFPR64Op>;
126 def _D : F_ACCUM_XYZ<1, sop, op, "d", opnode, sFPR64Op>;
132 def _D : F_CMPXY<1, sop, op, "d", sFPR64Op>;
139 def _D : F_CMPZX<1, sop, op, "d", sFPR64Op>;
235 def _D : F_XYAI_LD<sop, 1, op, "d", sFPR64Op, uimm8_2>;
241 def _D : F_XYAR_LD<sop, 1, op, "d", sFPR64Op>;
253 def _D : F_XYAR_ST<sop, 1, op, "d", sFPR64Op>;
261 def _D : F_I4_XY_MEM<sop, 1, (outs),
[all …]
H A DCSKYInstrFormatsF2.td39 def _D : F2_XYZ<0b00001, sop, op#".64"#"\t$vrz, $vrx, $vry",
50 def _D : F2_XYZ<0b00001, sop, op#".64"#"\t$vrz, $vrx, $vry",
81 def _D : F2_XZ<0b00001, FPR64Op, sop, op#".64", opnode>;
87 def _D : F2_XZ_SET<0b00001, FPR64Op, sop, op#".64"#suffix>;
100 def _D : F2_CXY<0b00001, FPR64Op, sop, op#".64">;
113 def _D : F2_CX<0b00001, FPR64Op, sop, op#".64">;
190 def _D : F2_CXYZ<0b00001, FPR64Op, sop, op#".64">;
H A DCSKYInstrInfoF2.td293 (Br (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
300 (MV (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2))>;
314 … (f2FSEL_D (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), FPR64Op:$rx, FPR64Op:$false),
315 … (f2FSEL_D (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), FPR64Op:$false, FPR64Op:$rx)
326 (Br (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), bb:$imm16)>;
333 (MV (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1))>;
347 … (f2FSEL_D (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), FPR64Op:$rx, FPR64Op:$false),
348 … (f2FSEL_D (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), FPR64Op:$false, FPR64Op:$rx)
H A DCSKYInstrInfoF1.td307 (Br (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;
314 (MV (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2))>;
323 (Br (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1), bb:$imm16)>;
330 (MV (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1))>;
/llvm-project-15.0.7/clang/test/Preprocessor/
H A Dpragma_microsoft.cpp3 #pragma warning(push, 4_D) // expected-warning {{requires a level between 0 and 4}}
/llvm-project-15.0.7/llvm/tools/bugpoint/
H A Dbugpoint.cpp103 AddToDriver(BugDriver &_D) : FunctionPassManager(nullptr), D(_D) {} in AddToDriver() argument
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Dnon-lazy-classes.m3 …ivate global [3 x {{.*}}]{{.*}}@"OBJC_CLASS_$_A"{{.*}},{{.*}}@"OBJC_CLASS_$_D"{{.*}},{{.*}}"OBJC_C…
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-collect-loh.ll278 ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _D@GOTPAGE
280 ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _D@GOTPAGEOFF]
291 ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _D@GOTPAGE
293 ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _D@GOTPAGEOFF]
307 ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _D@GOTPAGE
309 ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _D@GOTPAGEOFF]
324 ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _D@GOTPAGE
326 ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _D@GOTPAGEOFF]
/llvm-project-15.0.7/libcxx/test/libcxx/
H A Dnasty_macros.compile.pass.cpp31 #define _D NASTY_MACRO macro
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td174 // TODO: Match signaling comparison strict_fsetccs with FCMP_S*_D instructions.
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td221 def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>,
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td3857 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
3866 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td636 defm AMDGPUSample : AMDGPUSampleHelper_Clamp<"_D", "_d", []>;