Searched refs:Zero64 (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 2929 Register Zero64; in buildMultiply() local
2937 if (!Zero64) in buildMultiply()
2938 Zero64 = B.buildConstant(S64, 0).getReg(0); in buildMultiply()
2939 return Zero64; in buildMultiply()
3542 auto Zero64 = B.buildConstant(S64, 0); in legalizeUnsignedDIV_REM64Impl() local
3543 auto NegDenom = B.buildSub(S64, Zero64, Denom); in legalizeUnsignedDIV_REM64Impl()
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| H A D | SIInstrInfo.cpp | 5681 Register Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); in extractRsrcPtr() local
5688 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B64), Zero64) in extractRsrcPtr()
5701 .addReg(Zero64) in extractRsrcPtr()
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| H A D | AMDGPUISelLowering.cpp | 1752 SDValue Zero64 = DAG.getConstant(0, DL, VT); in LowerUDIVREM64() local
1758 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS); in LowerUDIVREM64()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 8166 Register Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); in emitExt128() local
8168 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64) in emitExt128()
8171 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64); in emitExt128()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 5949 auto Zero64 = MIRBuilder.buildConstant(S64, 0); in lowerU64ToF32BitOps() local
5956 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64); in lowerU64ToF32BitOps()
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