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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2310 // [ 4] "add $Zdn, $_Zdn, $imm";
2550 // [84] "decp $Zdn, $Pg";
2855 // [186] "incp $Zdn, $Pg";
2876 // [193] "insr $Zdn, $Rm";
2879 // [194] "insr $Zdn, $Vm";
3263 // [322] "mul $Zdn, $_Zdn, $imm";
3495 // [400] "sqdecp $Zdn, $Pg";
3537 // [414] "sqincp $Zdn, $Pg";
3709 // [472] "sub $Zdn, $_Zdn, $imm";
3808 // [508] "uqdecp $Zdn, $Pg";
[all …]
H A DSVEInstrFormats.td834 bits<5> Zdn;
1747 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
1749 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
1751 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
1754 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
1756 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
1758 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
1760 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
4526 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
4528 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1791 unsigned Zdn = fieldFromInstruction(insn, 0, 5); in DecodeSVELogicalImmInstruction() local
1797 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); in DecodeSVELogicalImmInstruction()
1799 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); in DecodeSVELogicalImmInstruction()