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Searched refs:ZW (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/ADT/
H A DAPIntTest.cpp3034 ZW = ZW2; in TEST()
3043 ZW |= ZW2; in TEST()
3044 ZW &= ZW2; in TEST()
3045 ZW ^= ZW2; in TEST()
3047 ZW &= 42; in TEST()
3048 ZW ^= 42; in TEST()
3053 ZW += ZW2; in TEST()
3058 ZW <<= 0; in TEST()
3064 EXPECT_EQ(1, ZW == ZW); in TEST()
3065 EXPECT_EQ(0, ZW != ZW); in TEST()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonDepIICHVX.td249 InstrItinData <tc_3ad719fb, /*SLOT01,ZW*/
487 InstrItinData <tc_a0dbea28, /*SLOT01,ZW*/
621 InstrItinData <tc_dd5b0695, /*SLOT01,ZW*/
653 InstrItinData <tc_e699ae41, /*SLOT01,ZW*/
813 InstrItinData <tc_3ad719fb, /*SLOT01,ZW*/
1051 InstrItinData <tc_a0dbea28, /*SLOT01,ZW*/
1185 InstrItinData <tc_dd5b0695, /*SLOT01,ZW*/
1217 InstrItinData <tc_e699ae41, /*SLOT01,ZW*/
1377 InstrItinData <tc_3ad719fb, /*SLOT01,ZW*/
1615 InstrItinData <tc_a0dbea28, /*SLOT01,ZW*/
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedExynosM5.td631 def : InstRW<[M5WriteAD], (instregex "^TBN?ZW")>;
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AMDGPU/
H A Damdgcn-intrinsics.ll1345 …@llvm.amdgcn.exp.compr.v2f16(i32 0, i32 12, <2 x half> undef, <2 x half> [[ZW:%.*]], i1 true, i1 f…
1346 …llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> [[XY]], <2 x half> [[ZW]], i1 true, i1 false)
/llvm-project-15.0.7/clang/include/clang/Driver/
H A DOptions.td6871 def _SLASH_ZW : CLJoined<"ZW">;