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Searched refs:ZIP1 (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h181 ZIP1, enumerator
H A DAArch64SchedKryoDetails.td2329 (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>;
2365 (instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>;
2377 (instregex "ZIP1(v4i32|v8i16|v16i8)")>;
H A DAArch64SchedFalkorDetails.td920 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|…
H A DAArch64SchedThunderX3T110.td1642 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
H A DAArch64ISelLowering.cpp2126 MAKE_CASE(AArch64ISD::ZIP1) in getTargetNodeName()
4583 return DAG.getNode(AArch64ISD::ZIP1, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
10208 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
10543 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; in LowerVECTOR_SHUFFLE()
10556 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; in LowerVECTOR_SHUFFLE()
21786 DAG, VT, DAG.getNode(AArch64ISD::ZIP1, DL, ContainerVT, Op1, Op2)); in LowerFixedLengthVECTOR_SHUFFLEToSVE()
21796 DAG, VT, DAG.getNode(AArch64ISD::ZIP1, DL, ContainerVT, Op1, Op1)); in LowerFixedLengthVECTOR_SHUFFLEToSVE()
H A DAArch64SchedA64FX.td1944 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
H A DAArch64InstrInfo.td590 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
5417 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-intrinsics-perm-select.ll1936 ; ZIP1