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Searched refs:ZIP (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/bolt/test/
H A Dbolt-icf.test14 CHECK-SYM-DAG: [[#%x,ZIP:]] T _Z3zipv
15 CHECK-SYM-DAG: [[#ZIP]] T _Z3zapv
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dpostlegalizer-lowering-trn.mir149 ; 2 x s32 TRN is redundant with ZIP. Make sure we prioritize ZIP.
173 ; 2 x s32 TRN is redundant with ZIP. Make sure we prioritize ZIP.
/llvm-project-15.0.7/clang/utils/analyzer/
H A DProjectMap.py16 ZIP = "zip" variable in DownloadType
H A DSATestBuild.py602 elif self.project.source == DownloadType.ZIP:
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-trn.ll82 ; 2xi32 TRN is redundant with ZIP
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td651 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(UZP|ZIP)[12]v")>;
H A DAArch64SchedExynosM3.td684 def : InstRW<[M3WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>;
H A DAArch64SchedA57.td564 def : InstRW<[A57Write_6cyc_3V], (instregex "^(UZP|ZIP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>;
H A DAArch64SchedNeoverseN2.td1552 def : InstRW<[N2Write_2cyc_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSDQ]$")>;
1884 def : InstRW<[N2Write_2cyc_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]$")>;
H A DAArch64SchedExynosM4.td835 def : InstRW<[M4WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>;
H A DAArch64SchedExynosM5.td870 def : InstRW<[M5WriteNSHF2], (instregex "^(TRN|UZP|ZIP)[12]v")>;