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Searched refs:Z5 (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dgep-expanded-vector.ll18 ; CHECK-NEXT: vpaddq [[Z1]], [[Z5:%zmm[0-9]]], [[Z5]]
/llvm-project-15.0.7/clang/test/Index/
H A Dindex-templates.cpp62 struct Z5 { struct
70 Z5 z5; in unresolved_exprs()
/llvm-project-15.0.7/clang/test/CXX/temp/temp.param/
H A Dp2.cpp26 template<extern int> struct Z5; //expected-error{{invalid declaration specifier}}
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dbad-reduction.ll31 ; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[T5]] to i64
39 ; CHECK-NEXT: [[SH5:%.*]] = shl nuw nsw i64 [[Z5]], 16
119 ; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[T5]] to i64
127 ; CHECK-NEXT: [[SH5:%.*]] = shl nuw nsw i64 [[Z5]], 16
209 ; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[LD5]] to i64
216 ; CHECK-NEXT: [[S5:%.*]] = shl nuw nsw i64 [[Z5]], 40
295 ; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[LD5]] to i64
303 ; CHECK-NEXT: [[S5:%.*]] = shl nuw nsw i64 [[Z5]], 40
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp39 AArch64::Z3, AArch64::Z4, AArch64::Z5,
H A DAArch64CallingConvention.td80 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>,
150 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>,
H A DAArch64RegisterInfo.td810 def Z5 : AArch64Reg<5, "z5", [Q5, Z5_HI]>, DwarfRegNum<[101]>;
/llvm-project-15.0.7/clang/unittests/StaticAnalyzer/
H A DRangeSetTest.cpp879 constexpr auto Z5 = TV::template X555TruncZeroOf<T>; in TYPED_TEST() local
880 this->template checkCastTo<F, T>({{XAAA, ZA}, {X555, Z5}}, in TYPED_TEST()
1068 constexpr auto Z5 = TV::template X555TruncZeroOf<T>; in TYPED_TEST() local
1069 this->template checkCastTo<F, T>({{XAAA, ZA}, {X555, Z5}}, in TYPED_TEST()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1290 case AArch64::Z4: Reg = AArch64::Z5; break; in getNextVectorRegister()
1291 case AArch64::Z5: Reg = AArch64::Z6; break; in getNextVectorRegister()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp2440 .Case("z5", AArch64::Z5) in matchSVEDataVectorRegName()