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/llvm-project-15.0.7/libcxx/test/libcxx/utilities/optional/optional.object/optional.object.assign/
H A Dcopy.pass.cpp40 struct Z2 struct
42 Z2() = default;
43 Z2(Z2&&) = default;
44 Z2(const Z2&) = delete;
45 Z2& operator=(Z2&&) = default;
46 Z2& operator=(const Z2&) = default;
75 static_assert(!(std::is_copy_assignable<optional<Z2>>::value), ""); in main()
H A Dmove.pass.cpp39 struct Z2 struct
41 Z2() = default;
42 Z2(Z2&&) = delete;
43 Z2& operator=(Z2&&) = default;
72 static_assert(!(std::is_move_assignable<optional<Z2>>::value), ""); in main()
/llvm-project-15.0.7/libcxx/test/std/utilities/meta/meta.trans/meta.trans.other/
H A Dcommon_reference.compile.pass.cpp45 struct Z2 {}; struct
50 using type = Z2;
54 using type = Z2;
154 static_assert(std::is_same_v<std::common_reference_t<X2&, Y2 const&>, Z2>);
186 …is_same_v<std::common_reference_t<std::tuple<int, X2>, std::tuple<int, Y2>>, std::tuple<int, Z2>>);
188 static_assert(!has_type<std::common_reference<std::tuple<int, const X2>, std::tuple<float, const Z2…
189 static_assert(!has_type<std::common_reference<std::tuple<int, X2>, std::tuple<float, Z2>>>);
214 …d::is_same_v<std::common_reference_t<std::pair<int, X2>, std::pair<int, Y2>>, std::pair<int, Z2>>);
215 …d::is_same_v<std::common_reference_t<std::pair<int, X2>, std::pair<int, Y2>>, std::pair<int, Z2>>);
216 static_assert(!has_type<std::common_reference<std::pair<int, const X2>, std::pair<float, const Z2>>…
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/PowerPC/
H A Dsplit-store-alignment.ll10 ; BE-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64
11 ; BE-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]]
23 ; LE-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64
24 ; LE-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]]
46 ; BE-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64
47 ; BE-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]]
59 ; LE-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64
60 ; LE-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]]
82 ; BE-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64
83 ; BE-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/X86/
H A Dsplit-store-alignment.ll12 ; CHECK-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64
13 ; CHECK-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]]
35 ; CHECK-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64
36 ; CHECK-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]]
58 ; CHECK-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64
59 ; CHECK-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]]
/llvm-project-15.0.7/clang/test/SemaTemplate/
H A Dfriend.cpp77 template<typename T> struct Z2 { struct
81 Z2<double> zd; // expected-note {{in instantiation of}}
82 Z2<int> z2i;
/llvm-project-15.0.7/clang/test/Index/
H A Dindex-templates.cpp20 struct Z2 { }; struct
23 class vector<Z2> {
30 using U::operator Z2;
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Daccessible-base.cpp23 struct Z2 : X2, A // expected-warning{{direct base 'A' is inaccessible due to ambiguity:\n struc… struct
44 A *z1_to_a(Z2 *p) { in z1_to_a()
H A Doverload-call.cpp306 struct Z2 : Z { }; struct
312 void db_rebind_test(Z2 z2) { in db_rebind_test()
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dmicrosoft-abi-rtti.cpp24 struct Z2 { virtual void f() {} }; in f() struct
26 struct A2 : Z2, Y2 {};
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dgep-expanded-vector.ll15 ; CHECK-NEXT: vpaddq [[Z1]], [[Z2:%zmm[0-9]]], [[Z2]]
/llvm-project-15.0.7/llvm/test/tools/llvm-pdbutil/Inputs/
H A DSimplePaddingTest.cpp132 virtual void Z2() {} in Z2() function
157 void Z2() override {} in Z2() function
/llvm-project-15.0.7/clang/test/Sema/
H A Dinvalid-bitwidth-expr.mm36 struct Z2 {
39 constexpr int sssss = sizeof(Z2); category
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Ddiv-shift.ll152 ; CHECK-NEXT: [[Z2:%.*]] = shl i8 1, [[Z:%.*]]
153 ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.umin.i8(i8 [[Y2]], i8 [[Z2]])
170 ; CHECK-NEXT: [[Z2:%.*]] = shl i8 1, [[Z:%.*]]
171 ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.smin.i8(i8 [[Y2]], i8 [[Z2]])
186 ; CHECK-NEXT: [[Z2:%.*]] = shl i8 1, [[Z:%.*]]
187 ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.smax.i8(i8 [[Y2]], i8 [[Z2]])
/llvm-project-15.0.7/llvm/test/Analysis/ScalarEvolution/
H A Dfold.ll35 %Z2 = select i1 %rand2, i32 %A, i32 %Z1
36 ; CHECK: %Z2 =
38 %B = trunc i32 %Z2 to i16
/llvm-project-15.0.7/flang/test/Fir/
H A Dtarget-rewrite-complex.fir254 // X64-DAG: fir.store [[Z2]] to [[Z2_ADDR]] : !fir.ref<!fir.vector<2:!fir.real<4>>>
282 // AARCH64-DAG: fir.store [[Z2]] to [[Z2_ARR]] : !fir.ref<!fir.array<2x!fir.real<4>>>
317 …// PPC-DAG: [[A2_EXTR:%[0-9A-Za-z]+]] = fir.extract_value [[Z2]], [0 : i32] : (!fir.complex<4>) ->…
318 …// PPC-DAG: [[B2_EXTR:%[0-9A-Za-z]+]] = fir.extract_value [[Z2]], [1 : i32] : (!fir.complex<4>) ->…
335 // X64-SAME: ([[Z1:%[0-9A-Za-z]+]]: !fir.vector<2:f32>, [[Z2:%[0-9A-Za-z]+]]: !fir.vector<2:f32>)
338 // AARCH64-SAME: ([[Z1:%[0-9A-Za-z]+]]: !fir.array<2xf32>, [[Z2:%[0-9A-Za-z]+]]: !fir.array<2xf32>)
347 …// I32-DAG: [[Z2_ADDR:%[0-9A-Za-z]+]] = fir.convert [[Z2]] : (!fir.ref<tuple<f32, f32>>) -> !fir.r…
360 // X64-DAG: fir.store [[Z2]] to [[Z2_ADDR]] : !fir.ref<!fir.vector<2:f32>>
380 // AARCH64-DAG: fir.store [[Z2]] to [[Z2_ARR]] : !fir.ref<!fir.array<2xf32>>
408 …// PPC-DAG: [[A2_EXTR:%[0-9A-Za-z]+]] = fir.extract_value [[Z2]], [0 : i32] : (complex<f32>) -> f32
[all …]
/llvm-project-15.0.7/clang/test/CXX/temp/temp.param/
H A Dp2.cpp23 template<virtual int Value> struct Z2; //expected-error{{invalid declaration specifier}}
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A DmemcmpIR.ll73 ; CHECK-NEXT: [[Z2:%[0-9]+]] = zext i1 [[CMP2]] to i32
74 ; CHECK-NEXT: [[SUB:%[0-9]+]] = sub i32 [[Z1]], [[Z2]]
83 ; CHECK-BE-NEXT: [[Z2:%[0-9]+]] = zext i1 [[CMP2]] to i32
84 ; CHECK-BE-NEXT: [[SUB:%[0-9]+]] = sub i32 [[Z1]], [[Z2]]
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/
H A Dpr32544.ll41 ; CHECK-NEXT: [[Z2:%.*]] = zext i32 [[SPEC_SELECT]] to i64
43 ; CHECK-NEXT: [[VALUE:%.*]] = add i64 [[C]], [[Z2]]
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A Daddrspacecast.ll31 ; CHECK-NEXT: [[Z2:%.*]] = addrspacecast i32* [[PTR]] to i32 addrspace(1)*
33 ; CHECK-NEXT: ret i32 addrspace(1)* [[Z2]]
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/ARM/
H A Dsink-free-instructions-inseltpoison.ll184 ; NEON-NEXT: [[Z2:%.*]] = zext <8 x i8> [[S2]] to <8 x i16>
185 ; NEON-NEXT: [[RES1:%.*]] = add <8 x i16> [[TMP0]], [[Z2]]
204 ; NONEON-NEXT: [[Z2:%.*]] = zext <8 x i8> [[S2]] to <8 x i16>
205 ; NONEON-NEXT: [[RES1:%.*]] = add <8 x i16> [[Z1]], [[Z2]]
H A Dsink-free-instructions.ll184 ; NEON-NEXT: [[Z2:%.*]] = zext <8 x i8> [[S2]] to <8 x i16>
185 ; NEON-NEXT: [[RES1:%.*]] = add <8 x i16> [[TMP0]], [[Z2]]
204 ; NONEON-NEXT: [[Z2:%.*]] = zext <8 x i8> [[S2]] to <8 x i16>
205 ; NONEON-NEXT: [[RES1:%.*]] = add <8 x i16> [[Z1]], [[Z2]]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Dmerge-cond-stores.ll150 ; CHECK-NEXT: [[Z2:%.*]] = add i32 [[Z1]], 24
151 ; CHECK-NEXT: [[Z3:%.*]] = and i32 [[Z2]], 67
329 ; CHECK-NEXT: [[Z2:%.*]] = phi i32 [ [[Z1]], [[NO1]] ], [ 0, [[YES1]] ]
337 ; CHECK-NEXT: [[Z3:%.*]] = sub i32 [[Z2]], [[B]]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dbad-reduction.ll28 ; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[T2]] to i64
36 ; CHECK-NEXT: [[SH2:%.*]] = shl nuw nsw i64 [[Z2]], 40
116 ; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[T2]] to i64
124 ; CHECK-NEXT: [[SH2:%.*]] = shl nuw nsw i64 [[Z2]], 40
206 ; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[LD2]] to i64
213 ; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i64 [[Z2]], 16
292 ; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[LD2]] to i64
300 ; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i64 [[Z2]], 16
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/AArch64/
H A Dsink-free-instructions-inseltpoison.ll162 ; CHECK-NEXT: [[Z2:%.*]] = zext <8 x i8> [[S2]] to <8 x i16>
163 ; CHECK-NEXT: [[RES1:%.*]] = add <8 x i16> [[TMP1]], [[Z2]]
208 ; CHECK-NEXT: [[Z2:%.*]] = zext <8 x i8> [[S2]] to <8 x i16>
209 ; CHECK-NEXT: [[RES1:%.*]] = add <8 x i16> [[TMP1]], [[Z2]]

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