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Searched refs:XW (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dctpop16.ll46 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
113 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
197 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
284 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1061 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1133 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1207 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1283 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1364 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1451 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
[all …]
H A Dstore-global.ll24 ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
44 ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
H A Dkernel-args.ll608 ; EG-NEXT: MEM_RAT MSKOR T4.XW, T5.X
639 ; CM-NEXT: MEM_RAT MSKOR T4.XW, T5.X
925 ; EG-NEXT: MEM_RAT MSKOR T4.XW, T7.X
926 ; EG-NEXT: MEM_RAT MSKOR T5.XW, T6.X
970 ; CM-NEXT: MEM_RAT MSKOR T4.XW, T7.X
971 ; CM-NEXT: MEM_RAT MSKOR T5.XW, T6.X
1065 ; EG-NEXT: MEM_RAT MSKOR T5.XW, T8.X
1100 ; CM-NEXT: MEM_RAT MSKOR T5.XW, T8.X
1747 ; EG-NEXT: MEM_RAT MSKOR T5.XW, T8.X
1795 ; CM-NEXT: MEM_RAT MSKOR T5.XW, T7.X
[all …]
H A Dr600.bitcast.ll148 ; EG-NEXT: MEM_RAT MSKOR T5.XW, T6.X
H A Dcttz_zero_undef.ll338 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
409 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
612 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
711 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1482 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1582 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
H A Dfp_to_uint.ll646 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
696 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
745 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
H A Dfp_to_sint.ll764 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
814 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
863 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
H A Dcttz.ll454 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1344 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1450 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1553 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
H A Dshl.ll184 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
258 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
335 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
431 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
502 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
H A Dctlz.ll528 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1570 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1691 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1814 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
H A Dctlz_zero_undef.ll353 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
914 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1017 ; EG-NEXT: MEM_RAT MSKOR T1.XW, T2.X
H A Dload-global-i16.ll63 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
89 ; CM-NEXT: MEM_RAT MSKOR T0.XW, T1.X
261 ; EG-NEXT: MEM_RAT MSKOR T5.XW, T8.X
296 ; CM-NEXT: MEM_RAT MSKOR T5.XW, T8.X
H A Dudiv.ll2442 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
H A Dload-constant-i16.ll60 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
198 ; EG-NEXT: MEM_RAT MSKOR T5.XW, T8.X
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedExynosM3.td553 def : InstRW<[M3WriteFCVT4A], (instregex "^[SU]CVTF[SU][XW][DHS]ri")>;
554 def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>;
H A DAArch64SchedAmpere1.td853 def : InstRW<[Ampere1Write_2cyc_1AB_1S_1Z], (instregex "^STR[BHSDQ]ro[XW]")>;
923 def : InstRW<[Ampere1Write_10cyc_1XY_1Z], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
H A DAArch64SchedExynosM4.td667 def : InstRW<[M4WriteFCVT6A], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>;
668 def : InstRW<[M4WriteNEONR], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
H A DAArch64SchedExynosM5.td724 def : InstRW<[M5WriteFCVTC], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>;
725 def : InstRW<[M5WriteFCVTB], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
H A DAArch64SchedA57.td578 def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?"…
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DEvergreenInstructions.td69 "MSKOR $rw_gpr.XW, $index_gpr",
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DScalarEvolution.cpp9915 APInt XW = X->sext(W); in MinOptional() local
9917 return XW.slt(YW) ? *X : *Y; in MinOptional()