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/llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/
H A Dmanual-shadow.ll11 ; RUN: --check-prefix=CHECK-XOR-AND %s
33 ; CHECK-XOR-LABEL: @read_value
34 ; CHECK-XOR-NOT: ret i32
35 ; CHECK-XOR: xor{{.*}}48879
36 ; CHECK-XOR-NEXT: add{{.*}}3735928559
37 ; CHECK-XOR: ret i32
39 ; CHECK-XOR-AND-LABEL: @read_value
40 ; CHECK-XOR-AND-NOT: ret i32
41 ; CHECK-XOR-AND: and{{.*}}-4294901761
42 ; CHECK-XOR-AND-NEXT: xor{{.*}}48879
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-xor.mir17 ; CHECK-NEXT: [[XOR:%[0-9]+]]:sgpr(s32) = G_XOR [[COPY]], [[COPY1]]
36 ; CHECK-NEXT: [[XOR:%[0-9]+]]:vgpr(s32) = G_XOR [[COPY2]], [[COPY1]]
55 ; CHECK-NEXT: [[XOR:%[0-9]+]]:vgpr(s32) = G_XOR [[COPY]], [[COPY2]]
99 ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[XOR]](s32)
128 ; CHECK-NEXT: S_NOP 0, implicit [[XOR]](s1)
157 ; CHECK-NEXT: S_NOP 0, implicit [[XOR]](s1)
237 ; CHECK-NEXT: S_NOP 0, implicit [[XOR]](s1)
278 ; CHECK-NEXT: [[XOR:%[0-9]+]]:vgpr(s32) = G_XOR [[UV]], [[UV2]]
370 ; CHECK-NEXT: S_NOP 0, implicit [[XOR]](s64)
584 ; CHECK-NEXT: S_NOP 0, implicit [[XOR]](<2 x s32>)
[all …]
H A Dlegalize-xor.mir15 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]]
16 ; CHECK-NEXT: $vgpr0 = COPY [[XOR]](s32)
34 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]]
35 ; CHECK-NEXT: S_NOP 0, implicit [[XOR]](s32)
133 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[XOR]](s64)
201 ; CHECK-NEXT: $vgpr0 = COPY [[XOR]](s32)
223 ; CHECK-NEXT: $vgpr0 = COPY [[XOR]](s32)
295 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[XOR]](s64)
317 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[XOR]](<2 x s32>)
439 ; CHECK-NEXT: $vgpr0 = COPY [[XOR]](<2 x s16>)
[all …]
H A Dcombine-or-redundant.mir90 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
91 ; CHECK-NEXT: $sgpr0 = COPY [[XOR]](s32)
118 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[LSHR]], [[C1]]
119 ; CHECK-NEXT: $vgpr0 = COPY [[XOR]](s32)
146 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[LSHR]], [[C1]]
147 ; CHECK-NEXT: $sgpr0 = COPY [[XOR]](s32)
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dlegalize-xor-scalar.mir47 ; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[TRUNC]], [[TRUNC1]]
72 ; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[DEF]], [[DEF]]
73 ; CHECK: $al = COPY [[XOR]](s8)
97 ; CHECK: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[DEF]], [[DEF]]
98 ; CHECK: $ax = COPY [[XOR]](s16)
122 ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[DEF]], [[DEF]]
123 ; CHECK: $eax = COPY [[XOR]](s32)
147 ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
148 ; CHECK: $rax = COPY [[XOR]](s64)
H A Dlegalize-fneg.mir26 ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[DEF]], [[C]]
27 ; CHECK: $edi = COPY [[XOR]](s32)
43 ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[C]]
44 ; CHECK: $rdi = COPY [[XOR]](s64)
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dprevent-cmp-merge.ll10 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[LHS:%.*]], 5
11 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[XOR]], 10
12 ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[XOR]], [[RHS:%.*]]
26 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[LHS:%.*]], 5
27 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[XOR]], 10
28 ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[XOR]], [[RHS:%.*]]
42 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[LHS:%.*]], [[RHS:%.*]]
43 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[XOR]], 0
44 ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[XOR]], 32
H A Dor-xor.ll319 ; CHECK-NEXT: ret i32 [[XOR]]
332 ; CHECK-NEXT: ret i32 [[XOR]]
346 ; CHECK-NEXT: ret i32 [[XOR]]
359 ; CHECK-NEXT: ret i32 [[XOR]]
375 ; CHECK-NEXT: ret i32 [[XOR]]
388 ; CHECK-NEXT: ret i9 [[XOR]]
438 ; CHECK-NEXT: ret i8 [[XOR]]
531 ; CHECK-NEXT: ret i32 [[XOR]]
546 ; CHECK-NEXT: ret i32 [[XOR]]
561 ; CHECK-NEXT: ret i32 [[XOR]]
[all …]
H A Dand-or-not.ll298 ; CHECK-NEXT: ret i32 [[XOR]]
311 ; CHECK-NEXT: ret i32 [[XOR]]
324 ; CHECK-NEXT: ret i32 [[XOR]]
337 ; CHECK-NEXT: ret i32 [[XOR]]
355 ; CHECK-NEXT: ret i32 [[XOR]]
374 ; CHECK-NEXT: ret i32 [[XOR]]
393 ; CHECK-NEXT: ret i32 [[XOR]]
412 ; CHECK-NEXT: ret i32 [[XOR]]
431 ; CHECK-NEXT: ret i32 [[XOR]]
450 ; CHECK-NEXT: ret i32 [[XOR]]
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h29 XOR = 0x06, enumerator
90 case XOR: in lanaiAluCodeToString()
111 .Case("xor", XOR) in stringToLanaiAluCode()
132 case ISD::XOR: in isdToLanaiAluCode()
133 return AluCode::XOR; in isdToLanaiAluCode()
/llvm-project-15.0.7/llvm/test/Transforms/Reassociate/
H A Dxor_reassoc.ll15 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[AND_RA]], 435
16 ; CHECK-NEXT: ret i32 [[XOR]]
30 ; CHECK-NEXT: ret <2 x i32> [[XOR]]
73 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 123
104 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 435
105 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[XOR]], [[AND]]
166 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[X:%.*]], 123
249 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[AND_RA]], 435
250 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[XOR]], [[OR]]
268 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[OR]], [[OR1]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-xor-01.ll1 ; Test vector XOR.
5 ; Test a v16i8 XOR.
14 ; Test a v8i16 XOR.
23 ; Test a v4i32 XOR.
32 ; Test a v2i64 XOR.
H A Dvec-xor-02.ll1 ; Test vector NOT-XOR on z14.
5 ; Test a v16i8 NOT-XOR.
18 ; Test a v8i16 NOT-XOR.
29 ; Test a v4i32 NOT-XOR.
39 ; Test a v2i64 NOT-XOR.
H A Datomicrmw-xor-02.ll7 ; Check XOR of a variable.
48 ; Check the minimum signed value. We XOR the rotated word with 0x80000000.
77 ; Check XORs of -1. We XOR the rotated word with 0xffff0000.
91 ; Check XORs of 1. We XOR the rotated word with 0x00010000.
105 ; Check the maximum signed value. We XOR the rotated word with 0x7fff0000.
119 ; Check XORs of a large unsigned value. We XOR the rotated word with
H A Datomicrmw-xor-01.ll7 ; Check XOR of a variable.
48 ; Check the minimum signed value. We XOR the rotated word with 0x80000000.
77 ; Check XORs of -1. We XOR the rotated word with 0xff000000.
91 ; Check XORs of 1. We XOR the rotated word with 0x01000000.
105 ; Check the maximum signed value. We XOR the rotated word with 0x7f000000.
119 ; Check XORs of a large unsigned value. We XOR the rotated word with
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-reduce-xor.mir45 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[UV]], [[UV1]]
47 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
79 ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[XOR]], [[XOR1]]
119 ; CHECK-NEXT: [[XOR4:%[0-9]+]]:_(s32) = G_XOR [[XOR]], [[XOR1]]
176 ; CHECK-NEXT: [[XOR8:%[0-9]+]]:_(s32) = G_XOR [[XOR]], [[XOR1]]
276 ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[XOR]], [[XOR1]]
314 ; CHECK-NEXT: [[XOR4:%[0-9]+]]:_(s32) = G_XOR [[XOR]], [[XOR1]]
530 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[UV]], [[UV1]]
531 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
614 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[UV]], [[UV1]]
[all …]
H A Dprelegalizercombiner-xor-of-and-with-same-reg.mir18 ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR %x, [[C]]
19 ; CHECK: %xor:_(s32) = G_AND [[XOR]], %y
43 ; CHECK: [[XOR:%[0-9]+]]:_(<2 x s32>) = G_XOR %x, [[BUILD_VECTOR]]
44 ; CHECK: %xor:_(<2 x s32>) = G_AND [[XOR]], %y
67 ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR %x, [[C]]
68 ; CHECK: %xor:_(s32) = G_AND [[XOR]], %y
91 ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR %x, [[C]]
92 ; CHECK: %xor:_(s32) = G_AND [[XOR]], %y
115 ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR %x, [[C]]
116 ; CHECK: %xor:_(s32) = G_AND [[XOR]], %y
H A Dlower-neon-vector-fcmp.mir293 ; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
322 ; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
401 ; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
428 ; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
455 ; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
482 ; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
509 ; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
536 ; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
563 ; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
590 ; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
[all …]
H A Dlegalize-fshr.mir18 ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]
19 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
50 ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY1]], [[C1]]
51 ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]]
H A Dlegalize-fshl.mir18 ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]
19 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
50 ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY1]], [[C1]]
51 ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]]
/llvm-project-15.0.7/llvm/test/Transforms/GVN/
H A Dassume.ll20 ; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[X:%.*]], true
21 ; CHECK-NEXT: call void @llvm.assume(i1 [[XOR]])
34 ; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[CMP]], true
35 ; CHECK-NEXT: call void @llvm.assume(i1 [[XOR]])
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dicmp.mir33 ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
34 ; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[XOR]], 1
59 ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
60 ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
289 ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
290 ; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[XOR]], 1
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dfptosi_and_fptoui.mir344 ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
359 ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
388 ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
405 ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
437 ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
454 ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
526 ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
541 ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
570 ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
587 ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
[all …]
H A Dcttz.mir15 ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]
17 ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
44 ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]
46 ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
86 ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C2]]
88 ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
126 ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C2]]
128 ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A DAndOrXor.ll560 ; CHECK-NEXT: ret i3 [[XOR]]
572 ; CHECK-NEXT: ret i32 [[XOR]]
596 ; CHECK-NEXT: ret i32 [[XOR]]
608 ; CHECK-NEXT: ret i32 [[XOR]]
620 ; CHECK-NEXT: ret i32 [[XOR]]
632 ; CHECK-NEXT: ret i32 [[XOR]]
644 ; CHECK-NEXT: ret i32 [[XOR]]
659 ; CHECK-NEXT: ret i32 [[XOR]]
672 ; CHECK-NEXT: ret i3 [[XOR]]
698 ; CHECK-NEXT: ret i32 [[XOR]]
[all …]

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