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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrKL.td19 let Uses = [XMM0, EAX], Defs = [EFLAGS] in {
22 [(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8XS,
26 let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in {
32 let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in {
68 let Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
69 Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
H A DX86CallingConv.td244 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
280 CCIfType<[f16], CCAssignToReg<[XMM0,XMM1,XMM2]>>,
306 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
334 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
343 CCIfType<[f16], CCAssignToReg<[XMM0, XMM1]>>,
344 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
345 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
346 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>,
348 // MMX vector types are always returned in XMM0.
349 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
[all …]
H A DX86AsmPrinter.cpp494 Index = Reg - X86::XMM0; in printAsmVRegister()
506 Reg = X86::XMM0 + Index; in printAsmVRegister()
H A DX86CallingConv.cpp80 static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2, in CC_X86_VectorCallGetSSEs()
H A DX86RegisterInfo.cpp612 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI) in getReservedRegs()
653 llvm::any_of(SmallVector<MCRegister>{X86::XMM0, X86::XMM1, X86::XMM2, in isArgumentRegister()
H A DX86CallLowering.cpp74 static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2, in assignArg()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dpr31143.ll4 ; CHECK: movss {{.*}}, %[[XMM0:xmm[0-9]+]]
6 ; CHECK: roundss $9, %[[XMM0]], %[[XMM1]]
31 ; CHECK: movsd {{.*}}, %[[XMM0:xmm[0-9]+]]
33 ; CHECK: roundsd $9, %[[XMM0]], %[[XMM1]]
H A Ddebuginfo-locations-dce.ll65 ; [0x0000000000000009, 0x0000000000000012): DW_OP_reg17 XMM0)
70 ; CHECK-NEXT: {{.*}}DW_OP_reg17 XMM0
H A Dx86-64-veccallcc.ll3 ; Test 1st and 2nd arguments passed in XMM0 and XMM1.
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DTargetTest.cpp196 setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)), in TEST_F()
202 IsMovValueFromStack(X86::MOVDQUrm, X86::XMM0), in TEST_F()
208 setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)), in TEST_F()
214 IsMovValueFromStack(X86::VMOVDQUrm, X86::XMM0), in TEST_F()
220 setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)), in TEST_F()
226 IsMovValueFromStack(X86::VMOVDQU32Z128rm, X86::XMM0), in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h344 return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM15); in isMem64_RC128()
347 return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM15); in isMem128_RC128()
353 return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM15); in isMem256_RC128()
360 return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM31); in isMem64_RC128X()
363 return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM31); in isMem128_RC128X()
369 return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM31); in isMem256_RC128X()
/llvm-project-15.0.7/llvm/test/TableGen/
H A DTargetInstrSpec.td47 def XMM0: Register<"xmm0">;
65 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
H A Dcast.td46 def XMM0: Register<"xmm0">;
64 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
H A DSlice.td40 def XMM0: Register<"xmm0">;
58 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
H A DMultiPat.td50 def XMM0: Register<"xmm0">;
68 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
/llvm-project-15.0.7/llvm/unittests/tools/llvm-mca/X86/
H A DX86TestBase.cpp23 .addReg(X86::XMM0)); in getSimpleInsts()
/llvm-project-15.0.7/llvm/test/DebugInfo/X86/
H A Dstack-value-piece.ll29 ; CHECK-NEXT: [{{.*}}, {{.*}}): DW_OP_reg17 XMM0, DW_OP_piece 0x4, {{(DW_OP_lit0, DW_OP_stack_v…
37 ; CHECK-NEXT: ({{.*}}, {{.*}}): DW_OP_reg17 XMM0, DW_OP_piece 0x4, {{DW_OP_lit0, DW_OP_stack_valu…
H A Dstack-value-piece-inseltpoison.ll29 ; CHECK-NEXT: [{{.*}}, {{.*}}): DW_OP_reg17 XMM0, DW_OP_piece 0x4, {{(DW_OP_lit0, DW_OP_stack_v…
37 ; CHECK-NEXT: ({{.*}}, {{.*}}): DW_OP_reg17 XMM0, DW_OP_piece 0x4, {{DW_OP_lit0, DW_OP_stack_valu…
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/
H A Dcallsite-stack-value.mir7 # CHECK-NEXT: DW_AT_location (DW_OP_reg17 XMM0)
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/Barcelona/
H A Dreg-move-elimination-1.s4 # The register move from XMM0 to XMM1 can be eliminated at register renaming
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/BdVer2/
H A Dreg-move-elimination-1.s4 # The register move from XMM0 to XMM1 can be eliminated at register renaming
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/BtVer2/
H A Dreg-move-elimination-1.s4 # The register move from XMM0 to XMM1 can be eliminated at register renaming
/llvm-project-15.0.7/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h216 ENTRY(XMM0) \
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp233 {codeview::RegisterId::XMM0, X86::XMM0}, in initLLVMToSEHAndCVRegMapping()
/llvm-project-15.0.7/llvm/test/MC/X86/
H A Dintel-syntax.s145 vshufpd XMM0, XMM1, XMM2, 1

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