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Searched refs:XADD (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/lib/TableGen/
H A DTGLexer.h55 XConcat, XADD, XSUB, XMUL, XNOT, XAND, XOR, XXOR, XSRA, XSRL, XSHL, enumerator
H A DTGLexer.cpp563 .Case("add", tgtok::XADD) in LexExclaim()
H A DTGParser.cpp1146 case tgtok::XADD: in ParseOperation()
1174 case tgtok::XADD: Code = BinOpInit::ADD; break; in ParseOperation()
1212 case tgtok::XADD: in ParseOperation()
2411 case tgtok::XADD: in ParseSimpleValue()
/llvm-project-15.0.7/llvm/test/CodeGen/BPF/
H A Dxadd.ll25 ; CHECK: line 4: Invalid usage of the XADD return value
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Datomic-flags.ll127 ; PR20841 - ensure we don't reuse the ZF flag from XADD for compares with zero,
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td622 // Atomic XADD for BPFNoALU32
623 class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
641 def XADDW : XADD<BPF_W, "u32", atomic_load_add_32>;
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ScheduleBtVer2.td429 // XADD %ecx, (%rsp) ## Instruction latency: 11cy
443 // XADD instructions. The second write of the sequence is JWriteXCHGrm_LdSt_Part.
447 // LOCK XADD %ecx, (%rsp) ## Instruction Latency: 16cy
H A DX86ScheduleZnver1.td799 // XADD.
801 def : InstRW<[ZnXADD], (instregex "XADD(8|16|32|64)rr")>;
802 def : InstRW<[WriteMicrocoded], (instregex "XADD(8|16|32|64)rm")>;
H A DX86ScheduleZnver2.td816 // XADD.
818 def : InstRW<[Zn2XADD], (instregex "XADD(8|16|32|64)rr")>;
819 def : InstRW<[WriteMicrocoded], (instregex "XADD(8|16|32|64)rm")>;
H A DX86ScheduleAtom.td624 def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm",
H A DX86SchedSandyBridge.td997 def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>;
H A DX86SchedSkylakeClient.td1217 def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
H A DX86SchedBroadwell.td1152 def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
H A DX86SchedHaswell.td1230 def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>;
H A DX86SchedSkylakeServer.td1486 def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
H A DX86SchedIceLake.td1500 def: InstRW<[ICXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
/llvm-project-15.0.7/llvm/docs/
H A DAtomics.rst440 uses ``XCHG``, ``atomicrmw add`` and ``atomicrmw sub`` use ``XADD``, and all