| /llvm-project-15.0.7/clang/test/CodeGen/ |
| H A D | override-layout.c | 96 struct PACKED X11 { struct 145 struct X11 x11; in use_structs() 146 typedef int X11array[sizeof(struct X11)]; in use_structs() 147 x11.y = sizeof(struct X11); in use_structs()
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| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/ |
| H A D | reserved-reg-errors.ll | 9 ; RUN: llc -mtriple=riscv32 -mattr=+reserve-x11 < %s 2>&1 | FileCheck %s -check-prefix=X11 10 ; RUN: llc -mtriple=riscv32 -mattr=+reserve-x11 < %s 2>&1 | FileCheck %s -check-prefix=X11 31 ; X11: warning: inline asm clobber list contains reserved registers: X11
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| H A D | reserved-regs.ll | 17 …lc -mtriple=riscv32 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11 18 …lc -mtriple=riscv64 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11 86 ; X11-NOT: lw a1, 87 ; X11-NOT: ld a1,
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| /llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/bugprone/ |
| H A D | copy-constructor-init.cpp | 138 class X11 : public Copyable5<int, float> { class 139 X11(const X11 &other) {} in X11() function in X11
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-reserve-call-saved-reg.ll | 9 …ux-gnu -mattr=+reserve-x11 -mattr=+call-saved-x11 -o - %s | FileCheck %s --check-prefixes=CHECK-X11 10 …=+reserve-x11 -mattr=+call-saved-x11 -global-isel -o - %s | FileCheck %s --check-prefixes=CHECK-X11 11 …tr=+reserve-x11 -mattr=+call-saved-x11 -fast-isel -o - %s | FileCheck %s --check-prefixes=CHECK-X11 41 ; CHECK-X11-NOT: str x11, [sp 53 ; CHECK-X11-NOT: ldr x11 61 ; CHECK-X11-NOT: str x11 70 ; CHECK-X11-NOT: ldr x11, [sp
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| H A D | arm64-custom-call-saved-reg.ll | 11 ; RUN: | FileCheck %s --check-prefix=CHECK-SAVED-X11 67 ; CHECK-SAVED-X11: str x11, [sp 93 ; CHECK-SAVED-X11: ldr x11, [sp 111 ; CHECK-SAVED-X11: adrp x11, var
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| H A D | arm64-platform-reg.ll | 18 …nux-gnu -mattr=+reserve-x11 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X11 83 ; RUN: --check-prefix=CHECK-RESERVE-X11 \ 125 ; CHECK-RESERVE-X11-NOT: ldr x11, 152 ; CHECK-RESERVE-X11-NOT: ldr x11,
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| /llvm-project-15.0.7/llvm/lib/ToolDrivers/llvm-dlltool/ |
| H A D | DlltoolDriver.cpp | 45 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \ argument 46 {X1, X2, X10, X11, OPT_##ID, llvm::opt::Option::KIND##Class, \
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| /llvm-project-15.0.7/lld/ELF/ |
| H A D | DriverUtils.cpp | 43 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \ argument 44 {X1, X2, X10, X11, OPT_##ID, opt::Option::KIND##Class, \
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| /llvm-project-15.0.7/clang/test/SemaCXX/ |
| H A D | new-delete.cpp | 275 struct X11 : X10 { struct 289 X11 x11; in f()
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| /llvm-project-15.0.7/llvm/test/MC/AArch64/ |
| H A D | armv8.4a-ldst-error.s | 57 STLUR X11, [SP, #256]
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| H A D | armv8.4a-ldst.s | 129 STLUR X11, [SP, #8]
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| /llvm-project-15.0.7/lld/MachO/ |
| H A D | DriverUtils.cpp | 44 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \ argument 45 {X1, X2, X10, X11, OPT_##ID, Option::KIND##Class, \
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| /llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/PowerPC/ |
| H A D | Target.cpp | 96 unsigned ScratchImmReg = PPC::X11; in setRegTo()
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| /llvm-project-15.0.7/llvm/lib/ToolDrivers/llvm-lib/ |
| H A D | LibDriver.cpp | 48 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \ argument 49 {X1, X2, X10, X11, OPT_##ID, opt::Option::KIND##Class, \
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| /llvm-project-15.0.7/lld/MinGW/ |
| H A D | Driver.cpp | 70 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \ argument 71 {X1, X2, X10, X11, OPT_##ID, opt::Option::KIND##Class, \
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 42 case AArch64::X11: return AArch64::W11; in getWRegFromXReg() 82 case AArch64::W11: return AArch64::X11; in getXRegFromWReg()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCSubtarget.h | 421 return IsPPC64 ? PPC::X11 : PPC::R11; in getEnvironmentPointerRegister()
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| H A D | PPCInstr64Bit.td | 1507 let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1509 let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1514 let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1516 let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1524 let Defs = [X0,X4,X5,X11,LR8,CR0] in 1535 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1565 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SLSHardening.cpp | 160 { "__llvm_slsblr_thunk_x11", AArch64::X11},
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| /llvm-project-15.0.7/lld/wasm/ |
| H A D | Driver.cpp | 110 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \ argument 111 {X1, X2, X10, X11, OPT_##ID, opt::Option::KIND##Class, \
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| /llvm-project-15.0.7/lld/COFF/ |
| H A D | DriverUtils.cpp | 793 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \ argument 794 {X1, X2, X10, X11, OPT_##ID, llvm::opt::Option::KIND##Class, \
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 115 {codeview::RegisterId::ARM64_X11, AArch64::X11}, in initLLVMToCVRegMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.td | 93 def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>;
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| H A D | RISCVFrameLowering.cpp | 879 RISCV::X10, RISCV::X11, /* a0-a1, a2-a7 */ in determineCalleeSaves()
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