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Searched refs:WriteMaskOp (Results 1 – 1 of 1) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp1875 const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1); in getShuffleComment() local
1876 if (WriteMaskOp.isReg()) { in getShuffleComment()
1877 CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}"; in getShuffleComment()