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Searched refs:WriteI (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DLiveInterval.cpp1181 WriteI = ReadI = LR->begin(); in add()
1191 if (ReadI != WriteI) in add()
1194 if (ReadI == WriteI) in add()
1198 *WriteI++ = *ReadI++; in add()
1228 if (WriteI != LR->begin() && coalescable(WriteI[-1], Seg)) { in add()
1229 WriteI[-1].end = std::max(WriteI[-1].end, Seg.end); in add()
1234 if (WriteI != ReadI) { in add()
1235 *WriteI++ = Seg; in add()
1240 if (WriteI == E) { in add()
1242 WriteI = ReadI = LR->end(); in add()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX.td53 def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
205 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
209 def THXT8XReadShifted : SchedReadAdvance<1, [WriteImm, WriteI,
213 def THXT8XReadNotShifted : SchedReadAdvance<2, [WriteImm, WriteI,
229 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
233 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
239 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
268 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedA53.td62 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
162 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
166 def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
170 def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
186 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
190 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
196 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
207 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedA55.td67 def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; } // ALU
219 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
224 def CortexA55ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
228 def CortexA55ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
243 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
247 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
253 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
272 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedThunderX2T99.td419 def : WriteRes<WriteI, [THX2T99I012]> {
425 def : InstRW<[WriteI],
438 def : InstRW<[WriteI], (instrs COPY)>;
585 // NOTE: Handled by WriteI.
602 // NOTE: Handled by WriteLD, WriteI.
723 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRBpost)>;
724 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRDpost)>;
725 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRHpost)>;
726 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRQpost)>;
727 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRSpost)>;
[all …]
H A DAArch64SchedKryo.td67 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
133 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedA57.td76 def : SchedAlias<WriteI, A57Write_1cyc_1I>;
134 def : InstRW<[WriteI], (instrs COPY)>;
149 SchedVar<NoSchedPred, [WriteI]>]>;
606 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>;
612 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>;
619 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>;
625 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>;
635 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>;
H A DAArch64Schedule.td24 def WriteI : SchedWrite; // ALU
H A DAArch64SchedFalkor.td72 def : WriteRes<WriteI, []> { let Unsupported = 1; }
H A DAArch64SchedA64FX.td814 def : WriteRes<WriteI, [A64FXGI2456]> {
819 def : InstRW<[WriteI],
832 def : InstRW<[WriteI], (instrs COPY)>;
974 // NOTE: Handled by WriteI.
991 // NOTE: Handled by WriteLD, WriteI.
1111 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRBpost)>;
1112 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRDpost)>;
1113 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRHpost)>;
1114 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRQpost)>;
1115 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRSpost)>;
[all …]
H A DAArch64SchedCyclone.td129 SchedVar<NoSchedPred, [WriteI]>]>;
153 def : WriteRes<WriteI, [CyUnitI]>;
296 def : InstRW<[WriteI], (instrs ISB)>;
364 def CyWriteCopyToGPR : WriteSequence<[WriteLD, WriteI]>;
H A DAArch64SchedThunderX3T110.td678 def : WriteRes<WriteI, [THX3T110I0123]> {
684 def : InstRW<[WriteI],
697 def : InstRW<[WriteI], (instrs COPY)>;
844 // NOTE: Handled by WriteI.
861 // NOTE: Handled by WriteLD, WriteI.
955 def : InstRW<[THX3T110Write_5Cyc_LS01_I0123, WriteI],
969 def : InstRW<[THX3T110Write_4Cyc_LS01_I0123_I0123, WriteI],
H A DAArch64SchedTSV110.td57 def : WriteRes<WriteI, [TSV110UnitALUAB]> { let Latency = 1; }
121 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64InstrFormats.td2016 Sched<[WriteI, ReadI]> {
2052 Sched<[WriteI, ReadI]> {
2080 Sched<[WriteI, ReadI, ReadI]> {
2104 Sched<[WriteI, ReadI, ReadI]> {
2358 Sched<[WriteI]> {
2422 Sched<[WriteI, ReadI]> {
2453 Sched<[WriteI, ReadI]> {
2479 Sched<[WriteI, ReadI, ReadI]>;
2895 Sched<[WriteI, ReadI]> {
2991 Sched<[WriteI, ReadI, ReadI]>;
[all …]
H A DAArch64SchedNeoverseN2.td614 def : InstRW<[WriteI], (instrs COPY)>;
635 def : SchedAlias<WriteI, N2Write_1cyc_1I>;
839 def : InstRW<[N2Write_6cyc_1I_1L, WriteI], (instregex "^LDR[BHSDQ]post$")>;
H A DAArch64SchedExynosM3.td199 def : SchedAlias<WriteI, M3WriteA1>;
H A DAArch64SchedAmpere1.td587 def : WriteRes<WriteI, [Ampere1UnitAB]>; // ALU
H A DAArch64SchedExynosM4.td512 def : SchedAlias<WriteI, M4WriteA1>;
H A DAArch64SchedExynosM5.td545 def : SchedAlias<WriteI, M5WriteA1W>;
H A DAArch64InstrInfo.td2482 Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>;
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DLiveInterval.h937 LiveRange::iterator WriteI; variable