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Searched refs:WIDTH (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DAMDHSAKernelDescriptor.h29 #define AMDHSA_BITS_ENUM_ENTRY(NAME, SHIFT, WIDTH) \ argument
31 NAME ## _WIDTH = (WIDTH), \
32 NAME = (((1 << (WIDTH)) - 1) << (SHIFT))
75 #define COMPUTE_PGM_RSRC1(NAME, SHIFT, WIDTH) \ argument
76 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_ ## NAME, SHIFT, WIDTH)
100 #define COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH) \ argument
101 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_ ## NAME, SHIFT, WIDTH)
127 #define COMPUTE_PGM_RSRC3_GFX90A(NAME, SHIFT, WIDTH) \ argument
139 #define COMPUTE_PGM_RSRC3_GFX10_PLUS(NAME, SHIFT, WIDTH) \ argument
152 #define KERNEL_CODE_PROPERTY(NAME, SHIFT, WIDTH) \ argument
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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dbfe-patterns.ll6 ; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
7 ; GCN: v_bfe_u32 v{{[0-9]+}}, [[SRC]], 0, [[WIDTH]]
24 ; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
25 ; GCN: v_sub_{{[iu]}}32_e32 [[SUB:v[0-9]+]], vcc, 32, [[WIDTH]]
49 ; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]]
64 ; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]]
80 ; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
81 ; GCN: v_bfe_i32 v{{[0-9]+}}, [[SRC]], 0, [[WIDTH]]
98 ; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
123 ; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]]
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H A Dimage-attributes.ll3 ; === WIDTH ==================================================================
/llvm-project-15.0.7/openmp/libomptarget/plugins/amdgpu/impl/
H A Dmsgpack.cpp25 #define X(NAME, WIDTH, PAYLOAD, LOWER, UPPER) \ in type_name() argument
37 #define X(NAME, WIDTH, PAYLOAD, LOWER, UPPER) \ in bytes_used_fixed() argument
39 return WIDTH; in bytes_used_fixed()
48 #define X(NAME, WIDTH, PAYLOAD, LOWER, UPPER) \ in parse_type() argument
163 #define X(NAME, WIDTH, PAYLOAD, LOWER, UPPER) \ in payload_info() argument
H A Dmsgpack.h111 #define X(NAME, WIDTH, PAYLOAD, LOWER, UPPER) NAME, argument
227 #define X(NAME, WIDTH, PAYLOAD, LOWER, UPPER) \ in handle_msgpack() argument
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/
H A Dloop-rotation-vs-common-code-hoisting.ll47 ; HOIST-NEXT: [[CMP:%.*]] = icmp slt i32 [[WIDTH:%.*]], 1
50 ; HOIST-NEXT: [[SUB:%.*]] = add nsw i32 [[WIDTH]], -1
69 ; ROTATE-NEXT: [[CMP:%.*]] = icmp slt i32 [[WIDTH:%.*]], 1
72 ; ROTATE-NEXT: [[CMP13_NOT:%.*]] = icmp eq i32 [[WIDTH]], 1
75 ; ROTATE-NEXT: [[TMP0:%.*]] = add i32 [[WIDTH]], -2
/llvm-project-15.0.7/libclc/generic/include/clc/shared/
H A Dvload.h1 #define _CLC_VLOAD_DECL(SUFFIX, MEM_TYPE, VEC_TYPE, WIDTH, ADDR_SPACE) \ argument
2 …_CLC_OVERLOAD _CLC_DECL VEC_TYPE vload##SUFFIX##WIDTH(size_t offset, const ADDR_SPACE MEM_TYPE *x);
H A Dvstore.h1 #define _CLC_VSTORE_DECL(SUFFIX, PRIM_TYPE, VEC_TYPE, WIDTH, ADDR_SPACE, RND) \ argument
2 …_CLC_OVERLOAD _CLC_DECL void vstore##SUFFIX##WIDTH##RND(VEC_TYPE vec, size_t offset, ADDR_SPACE PR…
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DLangOptions.h639 #define OPTION(NAME, TYPE, WIDTH, PREVIOUS) \ argument
642 static constexpr storage_type NAME##Width = WIDTH; \
648 #define OPTION(NAME, TYPE, WIDTH, PREVIOUS) +WIDTH argument
752 #define OPTION(NAME, TYPE, WIDTH, PREVIOUS) \ argument
859 #define OPTION(NAME, TYPE, WIDTH, PREVIOUS) \ argument
/llvm-project-15.0.7/clang/lib/Basic/
H A DLangOptions.cpp209 #define OPTION(NAME, TYPE, WIDTH, PREVIOUS) \ in getChangesSlow() argument
217 #define OPTION(NAME, TYPE, WIDTH, PREVIOUS) \ in dump() argument
224 #define OPTION(NAME, TYPE, WIDTH, PREVIOUS) \ in dump() argument
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dmemdep.ll2 …op-vectorize -force-vector-width=4 -force-vector-interleave=1 -S | FileCheck %s -check-prefix=WIDTH
69 ; WIDTH: f3_vec_len
70 ; WIDTH-NOT: <4 x i32>
/llvm-project-15.0.7/mlir/test/Conversion/GPUToNVVM/
H A Dgpu-to-nvvm.mlir125 // CHECK: %[[#WIDTH:]] = llvm.mlir.constant(23 : i32) : i32
130 // CHECK: %[[#NUM_LANES:]] = llvm.sub %[[#THIRTY_TWO]], %[[#WIDTH]] : i32
132 // CHECK: %[[#CLAMP:]] = llvm.sub %[[#WIDTH]], %[[#ONE]] : i32
140 // CHECK: %[[#NUM_LANES:]] = llvm.sub %[[#THIRTY_TWO]], %[[#WIDTH]] : i32
/llvm-project-15.0.7/mlir/test/Conversion/TosaToLinalg/
H A Dtosa-to-linalg-named.mlir220 // CHECK: [[WIDTH:%.+]] = arith.constant 32
226 // CHECK: [[NX:%.+]] = arith.subi [[WIDTH]], [[IDX2]]
/llvm-project-15.0.7/clang/lib/AST/
H A DJSONNodeDumper.cpp1698 #define OPTION(NAME, TYPE, WIDTH, PREVIOUS) \ in createFPOptions() argument
H A DTextNodeDumper.cpp757 #define OPTION(NAME, TYPE, WIDTH, PREVIOUS) \ in printFPOptions() argument
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AMDGPU/
H A Damdgcn-intrinsics.ll1042 …[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 [[OFFSET:%.*]], i32 [[WIDTH:%.*]])
1051 ; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 5, i32 [[WIDTH:%…
1103 ; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 1, i32 [[WIDTH:%…
1112 ; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 0, i32 [[WIDTH:%…
1121 ; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 0, i32 [[WIDTH:%…
1130 ; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 31, i32 [[WIDTH:…
1200 …EXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 undef, i32 [[WIDTH:%.*]])
1228 ; CHECK-NEXT: [[BFE:%.*]] = call i64 @llvm.amdgcn.ubfe.i64(i64 [[SRC:%.*]], i32 0, i32 [[WIDTH:%…
1253 ; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.sbfe.i32(i32 [[SRC:%.*]], i32 31, i32 [[WIDTH:…