Home
last modified time | relevance | path

Searched refs:W2 (Results 1 – 25 of 31) sorted by relevance

12

/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dweak-init.cpp8 extern const int W2 __attribute__((weak)) = 20;
10 int S2[W2]; // expected-error {{variable length array declaration not allowed at file scope}}
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/modernize/
H A Dpass-by-value.cpp256 struct W2 { struct
257 W2(const Movable &M, int) : M(M) {} in W2() argument
258 W2(Movable &&M, int);
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Dfexuprl.ll21 ; CHECK: fexupr.w $w[[W2:[0-9]+]], $w[[W0]]
22 ; CHECK: st.w $w[[W2]], 0(${{[0-9]+}})
/llvm-project-15.0.7/llvm/lib/Support/
H A DBinaryStreamWriter.cpp90 BinaryStreamWriter W2{Second}; in split() local
91 return std::make_pair(W1, W2); in split()
H A DBinaryStreamReader.cpp177 BinaryStreamReader W2{Second}; in split() local
178 return std::make_pair(W1, W2); in split()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFCallingConv.td37 CCIfType<[i32], CCAssignToRegWithShadow<[W1, W2, W3, W4, W5],
42 [W1, W2, W3, W4, W5]>>,
/llvm-project-15.0.7/llvm/lib/Transforms/IPO/
H A DThinLTOBitcodeWriter.cpp477 BitcodeWriter W2(Buffer); in splitAndWriteThinLTOBitcode() local
479 W2.writeThinLinkBitcode(M, Index, ModHash); in splitAndWriteThinLTOBitcode()
480 W2.writeModule(*MergedM, /*ShouldPreserveUseListOrder=*/false, in splitAndWriteThinLTOBitcode()
482 W2.writeSymtab(); in splitAndWriteThinLTOBitcode()
483 W2.writeStrtab(); in splitAndWriteThinLTOBitcode()
/llvm-project-15.0.7/libcxx/test/std/experimental/memory/memory.polymorphic.allocator.class/memory.polymorphic.allocator.mem/
H A Dconstruct_piecewise_pair_evil.pass.cpp110 template<class W1, class W2>
116 using Pair = std::pair<W1, W2>; in test_evil()
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dattr-mustprogress.cpp228 void W2() { in W2() function
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonCallingConv.td119 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
133 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
H A DHexagonGenInsert.cpp341 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()() local
342 for (uint16_t i = 0, w = std::min(W1, W2); i < w; ++i) { in operator ()()
348 if (W1 != W2) in operator ()()
349 return W1 < W2; in operator ()()
359 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()() local
368 return Bit2 < W2; in operator ()()
370 if (W2 <= Bit2) in operator ()()
H A DBitTracker.cpp697 uint16_t W1 = A1.width(), W2 = A2.width(); in eINS() local
699 assert(AtN < W1 && AtN+W2 <= W1); in eINS()
702 if (W2 > 0) in eINS()
703 Res.insert(RegisterCell::ref(A2), BT::BitMask(AtN, AtN+W2-1)); in eINS()
H A DHexagonRegisterInfo.cpp86 W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0 in getCallerSavedRegs()
H A DHexagonRegisterInfo.td234 def W2 : Rd< 4, "v5:4", [V4, V5, VF2]>, DwarfRegNum<[103]>;
273 def VQ1 : Rd< 4, "v7:4", [W2, W3]>, DwarfRegNum<[253]>;
/llvm-project-15.0.7/clang/test/CodeGenObjCXX/
H A Dblocks.mm83 __block Wrapper2 W2;
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/AArch64/
H A Ddbgcall-site-interpretation.mir17 # CHECK-NEXT: DW_AT_location (DW_OP_reg2 W2)
32 # W2 loads memory location. We can't rely that memory location won't be changed.
33 # CHECK-NOT: DW_AT_location (DW_OP_reg2 W2)
H A Ddbgcall-site-expr-entry-value.mir91 # CHECK-NEXT: DW_AT_location (DW_OP_reg2 W2)
H A Ddbgcall-site-expr-chain.mir107 # CHECK-NEXT: DW_AT_location (DW_OP_reg2 W2)
/llvm-project-15.0.7/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp113 BPF::W0, BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5,
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td93 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,
137 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,
205 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,
301 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,
H A DAArch64RegisterInfo.td70 def W2 : AArch64Reg<2, "w2" >, DwarfRegNum<[2]>;
105 def X2 : AArch64Reg<2, "x2", [W2]>, DwarfRegAlias<W2>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h33 case AArch64::X2: return AArch64::W2; in getWRegFromXReg()
73 case AArch64::W2: return AArch64::X2; in getXRegFromWReg()
/llvm-project-15.0.7/clang/test/Misc/
H A Ddiag-template-diffing.cpp1118 Wrapper<S<(&global2)>> W2 = MakeWrapper<S<&global>>();
1148 Wrapper<S<&global, static_cast<int*>(0)>> W2 = MakeWrapper<S<&global, ptr>>();
/llvm-project-15.0.7/mlir/test/Dialect/Shape/
H A Dcanonicalize.mlir485 // CHECK-NEXT: %[[W2:.*]] = "test.source"
486 // CHECK-NEXT: shape.assuming_all %[[W0]], %[[W1]], %[[W2]]
608 // CHECK-NEXT: %[[W2:.*]] = shape.assuming_all %[[W0]], %[[W1]]
609 // CHECK-NEXT: "consume.witness"(%[[W2]])
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp74 {codeview::RegisterId::ARM64_W2, AArch64::W2}, in initLLVMToCVRegMapping()

12