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Searched refs:W1 (Results 1 – 25 of 45) sorted by relevance

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/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/modernize/
H A Dpass-by-value.cpp251 struct W1 { struct
252 W1(const Movable &M) : M(M) {} in W1() function
253 W1(Movable &&M);
262 W3(const W1 &, const Movable &M) : M(M) {} in W3() argument
263 W3(W1 &&, Movable &&M);
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dweak-init.cpp3 extern const int W1 __attribute__((weak)) = 10; // expected-note {{declared here}}
5 static_assert(W1 == 10, ""); // expected-error {{static assertion expression is not an integral c…
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dmicrosoft-abi-rtti.cpp18 struct W1 : virtual V1 {}; struct
19 struct Y1 : W1, virtual V1 {} y1;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp369 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate() local
370 assert(W0 == 64 && W1 == 32); in evaluate()
372 RegisterCell RC = eADD(eSXT(CW, W1), rc(2)); in evaluate()
703 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate() local
708 .fill(W1+(W1-BX), W0, Zero); in evaluate()
710 RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1); in evaluate()
832 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate() local
833 assert(W0 == 64 && W1 == 32); in evaluate()
834 RegisterCell RC = eSXT(rc(1).cat(eIMM(0, W1)), W1); in evaluate()
864 uint16_t W1 = getRegBitWidth(Reg[1]); in evaluate() local
[all …]
H A DHexagonCallingConv.td119 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
133 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
H A DHexagonGenInsert.cpp341 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()() local
342 for (uint16_t i = 0, w = std::min(W1, W2); i < w; ++i) { in operator ()()
348 if (W1 != W2) in operator ()()
349 return W1 < W2; in operator ()()
359 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()() local
367 if (W1 <= Bit1) in operator ()()
H A DBitTracker.cpp697 uint16_t W1 = A1.width(), W2 = A2.width(); in eINS() local
698 (void)W1; in eINS()
699 assert(AtN < W1 && AtN+W2 <= W1); in eINS()
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darmv8.4a-ldst-error.s9 STLURB W1, [XZR, #1]
11 STLURB W1, [X10, #-257]
H A Darmv8.4a-ldst.s12 STLURB W1, [X10]
13 STLURB W1, [X10, #-256]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Dfexuprl.ll15 ; CHECK: fexupl.w $w[[W1:[0-9]+]], $w[[W0]]
16 ; CHECK: st.w $w[[W1]], 0(${{[0-9]+}})
H A Delm_insv.ll99 ; MIPS64-DAG: ld.d [[W1:\$w[0-9]+]],
102 ; MIPS64-DAG: insert.d [[W1]][1], [[R1]]
104 ; MIPS64-DAG: st.d [[W1]],
/llvm-project-15.0.7/llvm/lib/Support/
H A DBinaryStreamWriter.cpp89 BinaryStreamWriter W1{First}; in split() local
91 return std::make_pair(W1, W2); in split()
H A DBinaryStreamReader.cpp176 BinaryStreamReader W1{First}; in split() local
178 return std::make_pair(W1, W2); in split()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFCallingConv.td37 CCIfType<[i32], CCAssignToRegWithShadow<[W1, W2, W3, W4, W5],
42 [W1, W2, W3, W4, W5]>>,
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A D64-bit-vector.ll27 ; NO_SLP-NEXT: [[W1:%.*]] = getelementptr inbounds float, float* [[W]], i64 1
29 ; NO_SLP-NEXT: store float [[ADD1]], float* [[W1]], align 4
/llvm-project-15.0.7/libcxx/test/std/experimental/memory/memory.polymorphic.allocator.class/memory.polymorphic.allocator.mem/
H A Dconstruct_piecewise_pair_evil.pass.cpp110 template<class W1, class W2>
116 using Pair = std::pair<W1, W2>; in test_evil()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dbasic-promote-integers.ll79 %W1 = zext i16 %F1 to i64
81 %Y1 = insertelement <4 x i64> %Y0, i64 %W1, i32 2
/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/ELF/AArch64/
H A Ddisassemble-print-comments.s15 # DBGVARS-NEXT: ┠─ bar = W1
/llvm-project-15.0.7/clang/test/CodeGenObjCXX/
H A Dblocks.mm79 struct Wrapper2 { Wrapper1 W1; };
/llvm-project-15.0.7/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp113 BPF::W0, BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5,
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/AArch64/
H A Ddbgcall-site-interpretation.mir21 # CHECK-NEXT: DW_AT_location (DW_OP_reg1 W1)
34 # CHECK-NEXT: DW_AT_location (DW_OP_reg1 W1)
H A Ddbgcall-site-expr-chain.mir111 # CHECK-NEXT: DW_AT_location (DW_OP_reg1 W1)
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td93 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,
137 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,
205 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,
301 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h32 case AArch64::X1: return AArch64::W1; in getWRegFromXReg()
72 case AArch64::W1: return AArch64::X1; in getXRegFromWReg()
/llvm-project-15.0.7/clang/lib/Headers/
H A Dhexagon_types.h659 int W1(void) { in W1() function
756 HEXAGON_Vect64C W1(int w) { in W1() function
1886 int W1(void) { in W1() function
1983 Q6Vect64C W1(int w) { in W1() function

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