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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp325 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs); in evaluate()
327 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs); in evaluate()
394 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0)); in evaluate()
399 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0)); in evaluate()
645 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0); in evaluate()
654 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0); in evaluate()
734 assert(Wd < W0 && Of < W0); in evaluate()
736 if (Wd+Of > W0) in evaluate()
737 Wd = W0-Of; in evaluate()
752 return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs); in evaluate()
[all …]
H A DHexagonVectorPrint.cpp75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || in isVecReg()
186 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { in runOnMachineFunction()
187 LLVM_DEBUG(dbgs() << "adding dump for W" << Reg - Hexagon::W0 << '\n'); in runOnMachineFunction()
188 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, in runOnMachineFunction()
190 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, in runOnMachineFunction()
H A DHexagonCallingConv.td119 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
133 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
151 CCAssignToReg<[W0]>>>,
159 CCAssignToReg<[W0]>>>,
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dread_write_returned_arguments_scc.ll46 ; IS__TUNIT____-NEXT: ret i32* [[W0]]
56 ; IS__CGSCC____-NEXT: ret i32* [[W0]]
80 ; IS__TUNIT____-NEXT: store i32 1, i32* [[W0]], align 4
105 ; IS__CGSCC____-NEXT: store i32 1, i32* [[W0]], align 4
158 ; IS__TUNIT____-NEXT: store i32 [[ADD]], i32* [[W0]], align 4
186 ; IS__CGSCC____-NEXT: store i32 [[ADD]], i32* [[W0]], align 4
240 ; CHECK-NEXT: store i32 [[TMP0]], i32* [[W0]], align 4
243 ; CHECK-NEXT: ret i32* [[W0]]
274 ; IS__TUNIT____-NEXT: store i32 [[TMP1]], i32* [[W0]], align 4
296 ; IS__CGSCC____-NEXT: store i32 [[TMP1]], i32* [[W0]], align 4
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dno-odd-spreg-msa.ll36 ; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
37 ; NOODDSPREG: insve.w $w[[W0]][0], $w[[F0]][0]
38 ; ODDSPREG: insve.w $w[[W0]][0], $w13[0]
42 ; ALL: st.w $w[[W0]], 0($[[R0]])
72 ; ODDSPREG: insve.w $w[[W0]][1], $w13[0]
76 ; ALL: st.w $w[[W0]], 0($[[R0]])
99 ; ALL: move.v $w[[W0:13]], $w12
100 ; NOODDSPREG: move.v $w[[W0:12]], $w13
104 ; ALL: mov.s $f0, $f[[W0]]
128 ; NOODDSPREG: st.w $w[[W0]], 0($sp)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-unaligned_ldst.ll21 ; CHECK: ldr [[W0:w[0-9]+]], [x1]
22 ; CHECK: str [[W0]], [x0]
34 ; CHECK: ldrh [[W0:w[0-9]+]], [x1]
35 ; CHECK: strh [[W0]], [x0]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A D64-bit-vector.ll11 ; CHECK-NEXT: [[W0:%.*]] = getelementptr inbounds float, float* [[W:%.*]], i64 0
15 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float* [[W0]] to <2 x float>*
26 ; NO_SLP-NEXT: [[W0:%.*]] = getelementptr inbounds float, float* [[W:%.*]], i64 0
28 ; NO_SLP-NEXT: store float [[ADD0]], float* [[W0]], align 4
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Dfexuprl.ll14 ; CHECK: ld.h $w[[W0:[0-9]+]], 0(${{[0-9]+}})
15 ; CHECK: fexupl.w $w[[W1:[0-9]+]], $w[[W0]]
21 ; CHECK: fexupr.w $w[[W2:[0-9]+]], $w[[W0]]
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/AArch64/
H A Ddbgcall-site-interpret-movzxi.mir22 # CHECK-NEXT: DW_AT_location (DW_OP_reg0 W0)
28 # CHECK-NEXT: DW_AT_location (DW_OP_reg0 W0)
34 # CHECK-NEXT: DW_AT_location (DW_OP_reg0 W0)
40 # CHECK-NEXT: DW_AT_location (DW_OP_reg0 W0)
H A Ddbgcall-site-orr-moves.mir164 # CHECK-NEXT: DW_AT_location (DW_OP_reg0 W0)
165 # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_GNU_entry_value(DW_OP_reg0 W0))
210 # CHECK-NEXT: DW_AT_location (DW_OP_reg0 W0)
211 # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_GNU_entry_value(DW_OP_reg0 W0))
270 # CHECK-NEXT: DW_AT_location (DW_OP_reg0 W0)
H A Ddbgcall-site-indirect-param.mir27 # DWARF-NEXT: [0x0000000000000000, 0x0000000000000010): DW_OP_breg0 W0+0
28 # DWARF-NEXT: [0x0000000000000010, 0x000000000000001c): DW_OP_entry_value(DW_OP_reg0 W0))
H A Ddbgcall-site-interpretation.mir16 # CHECK-NOT: DW_AT_location (DW_OP_reg2 W0)
28 # CHECK-NEXT: DW_AT_location (DW_OP_reg0 W0)
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFCallingConv.td30 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [R0]>>,
31 CCIfType<[i64], CCAssignToRegWithShadow<[R0], [W0]>>
H A DBPFRegisterInfo.td41 W0, // Return value
/llvm-project-15.0.7/compiler-rt/lib/interception/
H A DCMakeLists.txt24 …append_list_if(COMPILER_RT_HAS_EXTERNAL_FLAG "/experimental:external /external:W0 /external:angleb…
/llvm-project-15.0.7/bolt/unittests/Core/
H A DMCPlusBuilder.cpp83 uint64_t AliasesX0[] = {AArch64::W0, AArch64::X0, AArch64::W0_W1, in TEST_P()
90 uint64_t AliasesX0[] = {AArch64::W0, AArch64::X0}; in TEST_P()
/llvm-project-15.0.7/compiler-rt/lib/builtins/
H A Dfp_div_impl.inc141 // C is (3/4 + 1/sqrt(2)) - 1 truncated to W0 fractional bits as UQ0.HW
142 // with W0 being either 16 or 32 and W0 <= HW.
161 // * C_hw being some (irrational) number **truncated** to W0 bits
165 // e_0 <= 3/4 - 1/sqrt(2) + 2^-W0
303 // W0 is the precision of C
304 // u_0 = (3/4 - 1/sqrt(2) + 2^-W0) * 2^HW
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-leaf-compact-unwind.s203 ; kill: def W0 killed W0 def X0
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp262 static_assert(AArch64::W30 - AArch64::W0 + 1 == N_GPR_REGS, "Number of GPRs"); in mapRegToGPRIndex()
265 if (AArch64::W0 <= Reg && Reg <= AArch64::W30) in mapRegToGPRIndex()
266 return Reg - AArch64::W0; in mapRegToGPRIndex()
H A DAArch64CallingConvention.td93 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,
137 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,
205 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,
289 // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0).
291 CCIfType<[i32], CCAssignToReg<[W0]>>,
301 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dbasic-promote-integers.ll78 %W0 = zext i16 %F0 to i64
80 %Y0 = insertelement <4 x i64> %A, i64 %W0, i32 0
/llvm-project-15.0.7/lldb/source/API/
H A DCMakeLists.txt129 set_property(SOURCE ${lldb_python_wrapper} APPEND_STRING PROPERTY COMPILE_FLAGS " /W0")
151 set_property(SOURCE ${lldb_lua_wrapper} APPEND_STRING PROPERTY COMPILE_FLAGS " /W0")
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dlivephysregs-regmask-clobber.mir3 # The PS_vstorerw_ai of W0 would normally expand into stores of V0 and V1,
/llvm-project-15.0.7/llvm/test/DebugInfo/AArch64/
H A Ddagcombine-zext.ll2 ; CHECK: DW_OP_reg0 W0
/llvm-project-15.0.7/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp113 BPF::W0, BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5,

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