| /llvm-project-15.0.7/clang/lib/Headers/ |
| H A D | hvx_hexagon_protos.h | 283 #define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv) argument
327 #define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv) argument
393 #define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv) argument
470 #define Q6_Vw_vadd_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)(Vu,Vv) argument
558 #define Q6_V_vand_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)(Vu,Vv) argument
624 #define Q6_Vh_vasl_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)(Vu,Vv) argument
657 #define Q6_Vw_vasl_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)(Vu,Vv) argument
822 #define Q6_Vh_vavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)(Vu,Vv) argument
888 #define Q6_Vw_vavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)(Vu,Vv) argument
2428 #define Q6_V_vor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)(Vu,Vv) argument
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatternsV65.td | 14 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
24 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
34 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
49 RC1:$Vv),
60 RC1:$Vv),
71 RC1:$Vv),
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| H A D | HexagonISelDAGToDAGHVX.cpp | 2367 SDValue Vv = N->getOperand(0); in selectVAlign() local
2371 N->getValueType(0), {Vv, Vu, Rt}); in selectVAlign()
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| /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/ |
| H A D | vgather-opt-addr.ll | 32 define dso_local void @contiguos_vgather_test(i32 %Rb, i32 %mu, i32 %nloops, <32 x i32> %Vv, <64 x …
60 call void @llvm.hexagon.V6.vgathermh.128B(i8* nonnull %0, i32 %Rb, i32 %mu, <32 x i32> %Vv)
61 call void @llvm.hexagon.V6.vgathermw.128B(i8* nonnull %1, i32 %Rb, i32 %mu, <32 x i32> %Vv)
63 …d @llvm.hexagon.V6.vgathermhq.128B(i8* nonnull %3, <128 x i1> %4, i32 %Rb, i32 %mu, <32 x i32> %Vv)
64 …d @llvm.hexagon.V6.vgathermwq.128B(i8* nonnull %5, <128 x i1> %4, i32 %Rb, i32 %mu, <32 x i32> %Vv)
|
| /llvm-project-15.0.7/lldb/test/API/functionalities/postmortem/FreeBSDKernel/ |
| H A D | vmcore-arm64-minidump.bz2 | 1minidump FreeBSD/arm64�������� ����j������������ |
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedExynosM4.td | 742 def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>;
748 def : InstRW<[M4WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>;
793 def : InstRW<[M4WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>;
|
| H A D | AArch64SchedExynosM5.td | 790 def : InstRW<[M5WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>;
796 def : InstRW<[M5WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>;
835 def : InstRW<[M5WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>;
|
| H A D | AArch64SchedExynosM3.td | 624 def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>;
654 def : InstRW<[M3WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>;
|
| H A D | AArch64SchedA55.td | 431 def : InstRW<[CortexA55WriteAluVq_4], (instregex "[SU](MAX|MIN)Vv")>;
|
| H A D | AArch64SchedTSV110.td | 636 def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(MAX|MIN)(NM)?Vv")>;
|
| H A D | AArch64SchedAmpere1.td | 910 def : InstRW<[Ampere1Write_10cyc_2XY], (instregex "^F(MAX|MIN)(NM)?Vv.[if](32|64)")>;
|
| H A D | AArch64SchedA57.td | 491 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
|