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Searched refs:Vt (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPatternsHVX.td280 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
282 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
561 def: Pat<(mul HVI8:$Vs, HVI8:$Vt),
564 def: Pat<(mul HVI16:$Vs, HVI16:$Vt),
566 def: Pat<(mul HVI32:$Vs, HVI32:$Vt),
658 def: Pat<(shl HVI16:$Vs, HVI16:$Vt), (V6_vaslhv HvxVR:$Vs, HvxVR:$Vt)>;
659 def: Pat<(shl HVI32:$Vs, HVI32:$Vt), (V6_vaslwv HvxVR:$Vs, HvxVR:$Vt)>;
660 def: Pat<(sra HVI16:$Vs, HVI16:$Vt), (V6_vasrhv HvxVR:$Vs, HvxVR:$Vt)>;
661 def: Pat<(sra HVI32:$Vs, HVI32:$Vt), (V6_vasrwv HvxVR:$Vs, HvxVR:$Vt)>;
662 def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;
[all …]
H A DHexagonISelLoweringHVX.cpp1708 SDValue Vt = Op.getOperand(1); in LowerHvxMulh() local
1722 SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG); in LowerHvxMulh()
1737 auto MulHS_V60 = [&](SDValue Vs, SDValue Vt) { in LowerHvxMulh() argument
1752 SDValue T0 = getInstr(Hexagon::V6_vmpyewuh, dl, ResTy, {Vt, Vs}, DAG); in LowerHvxMulh()
1756 {T0, S0, Vt}, DAG); in LowerHvxMulh()
1766 auto MulHS_V62 = [&](SDValue Vs, SDValue Vt) { in LowerHvxMulh() argument
1770 {T0, Vs, Vt}, DAG); in LowerHvxMulh()
1776 return MulHS_V62(Vs, Vt); in LowerHvxMulh()
1777 return MulHS_V60(Vs, Vt); in LowerHvxMulh()
1795 SDValue T0 = getInstr(Hexagon::V6_vmpyuhv, dl, PairTy, {Vs, Vt}, DAG); in LowerHvxMulh()
[all …]
H A DHexagonPatterns.td105 def valign: PatFrag<(ops node:$Vt, node:$Vs, node:$Ru),
106 (HexagonVALIGN node:$Vt, node:$Vs, node:$Ru)>;
347 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)),
348 CmpPred:$Vt, CmpPred:$Vs),
349 (PickT CmpPred:$Vs, CmpPred:$Vt)>;
350 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)),
351 CmpPred:$Vs, CmpPred:$Vt),
352 (PickS CmpPred:$Vs, CmpPred:$Vt)>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td9775 bits<5> Vt;
9785 let Inst{4-0} = Vt;
9791 bits<5> Vt;
9803 let Inst{4-0} = Vt;
9831 // "ld1\t$Vt, [$Rn]"
10080 bits<5> Vt;
10088 let Inst{4-0} = Vt;
10095 bits<5> Vt;
10103 let Inst{4-0} = Vt;
10157 // "ld1r.8b\t$Vt, [$Rn]"
[all …]
H A DAArch64InstrInfo.td3391 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
3396 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
3529 (STR (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
6988 : Pat<(store ty:$Vt, GPR64sp:$Rn),
6989 (INST ty:$Vt, GPR64sp:$Rn)>;
7150 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
7167 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
7183 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
7189 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
7209 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
[all …]
/llvm-project-15.0.7/openmp/runtime/src/
H A Dkmp_barrier.cpp29 #define ngo_load(src) __m512d Vt = _mm512_load_pd((void *)(src))
30 #define ngo_store_icvs(dst, src) _mm512_storenrngo_pd((void *)(dst), Vt)
31 #define ngo_store_go(dst, src) _mm512_storenrngo_pd((void *)(dst), Vt)
/llvm-project-15.0.7/llvm/lib/TableGen/
H A DTGParser.cpp2086 if (TypedInit *Vt = dyn_cast<TypedInit>(V)) in ParseOperationCond() local
2087 VTy = Vt->getType(); in ParseOperationCond()