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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2651 (Ty (ShOp (Ty DPR:$Vn),
2663 (Ty (ShOp (Ty DPR:$Vn),
2750 (Ty (IntOp (Ty DPR:$Vn),
2762 (Ty (IntOp (Ty DPR:$Vn),
3071 (TyQ (OpNode (TyD DPR:$Vn),
3080 (TyQ (OpNode (TyD DPR:$Vn),
5247 let Inst{19-16} = Vn{4-1};
5248 let Inst{7} = Vn{0};
7204 "vtbx", "8", "$Vd, $Vn, $Vm",
7209 "vtbx", "8", "$Vd, $Vn, $Vm",
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H A DARMInstrCDE.td430 iname#"\t$coproc, $Vd, $Vn, $Vm, $imm", params.Cstr> {
444 bits<5> Vn;
447 let Inst{19-16} = Vn{4-1};
449 let Inst{7} = Vn{0};
460 bits<5> Vn;
463 let Inst{19-16} = Vn{3-0};
465 let Inst{7} = Vn{4};
475 let Rn = (ins regclass:$Vn);
H A DARMInstrFormats.td2438 bits<5> Vn;
2444 let Inst{7} = Vn{4};
2455 bits<5> Vn;
2462 let Inst{7} = Vn{4};
2483 bits<5> Vn;
2504 bits<5> Vn;
2532 bits<5> Vn;
2657 bits<5> Vn;
2686 bits<5> Vn;
2709 // if Q == ‘1’ then UInt(N:Vn) else UInt(Vn:N);
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td4423 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
4425 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
4502 (UQXTNv8i8 V128:$Vn)>;
4505 (UQXTNv4i16 V128:$Vn)>;
4510 (SQXTNv8i8 V128:$Vn)>;
4513 (SQXTNv8i8 V128:$Vn)>;
4518 (SQXTNv4i16 V128:$Vn)>;
4521 (SQXTNv4i16 V128:$Vn)>;
6083 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
6088 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
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H A DAArch64InstrFormats.td7642 bits<5> Vn;
7652 let Inst{9-5} = Vn;
7663 bits<5> Vn;
7673 let Inst{9-5} = Vn;
11054 bits<5> Vn;
11056 let Inst{9-5} = Vn;
11071 : CryptoRRTied<op0, op1, asm, "{\t$Vd.2d, $Vn.2d|.2d\t$Vd, $Vn}">;
11073 : CryptoRRTied<op0, op1, asm, "{\t$Vd.4s, $Vn.4s|.4s\t$Vd, $Vn}">;
11088 "{\t$Vd.2d, $Vn.2d, $Vm.2d|.2d\t$Vd, $Vn, $Vm}", "">;
11094 "{\t$Vd.4s, $Vn.4s, $Vm.4s|.4s\t$Vd, $Vn, $Vm}", "">;
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H A DAArch64SchedCyclone.td336 // ORR.16b Vd,Vn,Vn
H A DSVEInstrFormats.td6683 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn),
6684 asm, "\t$Zd, $Pg/m, $Vn",
6688 bits<5> Vn;
6694 let Inst{9-5} = Vn;
6708 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
6709 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>;
6710 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
6711 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>;
6712 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
6713 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn), 1>;
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H A DAArch64SchedA64FX.td2517 // [73] "cpy $Zd, $Pg/m, $Vn";
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dcde-fp-vec.txt77 # Vector variant, Vn<0> == 1
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUOperandSyntax.rst90 **[Vm**, \ **Vn**, ... **Vk**\ **]** A sequence of 32-bit *vector* registers.
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp6134 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); in DecodeNEONComplexLane64Instruction() local
6135 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); in DecodeNEONComplexLane64Instruction()
6149 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) in DecodeNEONComplexLane64Instruction()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrFormats.td173 // bits<5> Vn : vector register input or output for operand n