| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 2511 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2517 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2526 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2533 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2576 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2585 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2594 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2603 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
3173 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3180 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
[all …]
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| H A D | ARMInstrCDE.td | 375 bits<5> Vm;
379 let Inst{3-0} = Vm{4-1};
380 let Inst{5} = Vm{0};
388 bits<5> Vm;
392 let Inst{3-0} = Vm{3-0};
393 let Inst{5} = Vm{4};
443 bits<5> Vm;
450 let Inst{5} = Vm{0};
451 let Inst{3-0} = Vm{4-1};
459 bits<5> Vm;
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| H A D | ARMInstrFormats.td | 2331 bits<5> Vm;
2346 bits<5> Vm;
2384 bits<5> Vm;
2406 bits<5> Vm;
2439 bits<5> Vm;
2456 bits<5> Vm;
2484 bits<5> Vm;
2505 bits<5> Vm;
2533 bits<5> Vm;
2604 bits<5> Vm;
[all …]
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/ |
| H A D | cde-fp-vec.txt | 51 # VCX2 Vector variant, Vm<0> == 1
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.td | 5422 (UZP1v16i8 V128:$Vn, V128:$Vm)>;
5425 (UZP1v8i16 V128:$Vn, V128:$Vm)>;
5428 (UZP1v4i32 V128:$Vn, V128:$Vm)>;
5433 (UZP2v16i8 V128:$Vn, V128:$Vm)>;
6083 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
6088 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
8238 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
8242 OutPatFrag<(ops node:$Vm, node:$Vn),
8246 (v8i8 node:$Vm),
8253 (odot_v8i8<DOT> V64:$Vm, V64:$Vn)>,
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| H A D | AArch64InstrFormats.td | 7643 bits<5> Vm;
7647 let Inst{20-16} = Vm;
7664 bits<5> Vm;
7668 let Inst{20-16} = Vm;
11078 bits<5> Vm;
11080 let Inst{20-16} = Vm;
11088 "{\t$Vd.2d, $Vn.2d, $Vm.2d|.2d\t$Vd, $Vn, $Vm}", "">;
11094 "{\t$Vd.4s, $Vn.4s, $Vm.4s|.4s\t$Vd, $Vn, $Vm}", "">;
11105 bits<5> Vm;
11127 bits<5> Vm;
[all …]
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| H A D | SVEInstrFormats.td | 1501 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcOpType:$Vm),
1502 asm, "\t$Zdn, $Vm",
1505 bits<5> Vm;
1510 let Inst{9-5} = Vm;
1523 def : Pat<(nxv8f16 (op nxv8f16:$Zn, f16:$Vm)),
1525 def : Pat<(nxv4f32 (op nxv4f32:$Zn, f32:$Vm)),
1527 def : Pat<(nxv2f64 (op nxv2f64:$Zn, f64:$Vm)),
1530 def : Pat<(nxv8bf16 (op nxv8bf16:$Zn, bf16:$Vm)),
1535 (!cast<Instruction>(NAME # _B) $Zn, ZPR:$Vm)>;
1537 (!cast<Instruction>(NAME # _H) $Zn, ZPR:$Vm)>;
[all …]
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| H A D | AArch64SchedA64FX.td | 2879 // [194] "insr $Zdn, $Vm";
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 6018 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeVCVTD() local
6019 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); in DecodeVCVTD()
6062 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeVCVTD()
6077 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeVCVTQ() local
6078 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); in DecodeVCVTQ()
6121 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeVCVTQ()
6136 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeNEONComplexLane64Instruction() local
6137 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); in DecodeNEONComplexLane64Instruction()
6151 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeNEONComplexLane64Instruction()
|
| /llvm-project-15.0.7/llvm/docs/ |
| H A D | AMDGPUOperandSyntax.rst | 90 **[Vm**, \ **Vn**, ... **Vk**\ **]** A sequence of 32-bit *vector* registers.
|