Searched refs:VecIns (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 723 auto *VecIns = dyn_cast<IntrinsicInst>(DupQLane->getArgOperand(0)); in instCombineSVECmpNE() local
724 if (!VecIns || VecIns->getIntrinsicID() != Intrinsic::vector_insert) in instCombineSVECmpNE()
729 if (!isa<UndefValue>(VecIns->getArgOperand(0))) in instCombineSVECmpNE()
732 if (!cast<ConstantInt>(VecIns->getArgOperand(2))->isZero()) in instCombineSVECmpNE()
735 auto *ConstVec = dyn_cast<Constant>(VecIns->getArgOperand(1)); in instCombineSVECmpNE()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 23550 SmallVector<SDValue, 8> VecIns; in MatchVectorAllZeroTest() local
23551 if (Op.getOpcode() == ISD::OR && matchScalarReduction(Op, ISD::OR, VecIns)) { in MatchVectorAllZeroTest()
23552 EVT VT = VecIns[0].getValueType(); in MatchVectorAllZeroTest()
23553 assert(llvm::all_of(VecIns, in MatchVectorAllZeroTest()
23562 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; in MatchVectorAllZeroTest()
23566 SDValue LHS = VecIns[Slot]; in MatchVectorAllZeroTest()
23567 SDValue RHS = VecIns[Slot + 1]; in MatchVectorAllZeroTest()
23568 VecIns.push_back(DAG.getNode(ISD::OR, DL, VT, LHS, RHS)); in MatchVectorAllZeroTest()
23572 if (SDValue V = LowerVectorAllZero(DL, VecIns.back(), CC, Mask, Subtarget, in MatchVectorAllZeroTest()
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