| /llvm-project-15.0.7/llvm/unittests/ADT/ |
| H A D | PackedVectorTest.cpp | 51 EXPECT_FALSE(Vec == Vec2); in TEST()
52 EXPECT_TRUE(Vec != Vec2); in TEST()
54 Vec = Vec2; in TEST()
55 EXPECT_TRUE(Vec == Vec2); in TEST()
56 EXPECT_FALSE(Vec != Vec2); in TEST()
59 Vec2[1] = 2; in TEST()
60 Vec |= Vec2; in TEST()
77 Vec2[0] = 0; in TEST()
78 Vec2[0] = 7; in TEST()
92 Vec2[0] = -4; in TEST()
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| /llvm-project-15.0.7/clang/test/CodeGen/ |
| H A D | arm_function_epilog.cpp | 4 struct Vec2 { struct
12 Vec2 getVec2() { in getVec2()
13 Vec2 out; in getVec2()
14 union { Vec2* v; unsigned char* u; } x; in getVec2()
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| /llvm-project-15.0.7/clang/test/AST/HLSL/ |
| H A D | vector-constructors.hlsl | 8 float2 Vec2 = float2(1.0, 2.0);
9 float3 Vec3 = float3(Vec2, 3.0);
14 // CHECK: VarDecl 0x{{[0-9a-fA-F]+}} <col:3, col:32> col:10 used Vec2 'float2':'float __attribute__…
31 …float __attribute__((ext_vector_type(2)))' lvalue Var 0x{{[0-9a-fA-F]+}} 'Vec2' 'float2':'float __…
35 …float __attribute__((ext_vector_type(2)))' lvalue Var 0x{{[0-9a-fA-F]+}} 'Vec2' 'float2':'float __…
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| H A D | vector-alias.hlsl | 24 hlsl::vector<float, 2> Vec2 = {1.0, 2.0};
27 …// CHECK-NEXT: VarDecl 0x{{[0-9a-fA-F]+}} <col:3, col:42> col:26 Vec2 'hlsl::vector<float, 2>':'fl…
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| /llvm-project-15.0.7/clang/lib/AST/ |
| H A D | ASTStructuralEquivalence.cpp | 811 const auto *Vec2 = cast<DependentSizedExtVectorType>(T2); in IsStructurallyEquivalent() local
813 Vec2->getSizeExpr())) in IsStructurallyEquivalent()
816 Vec2->getElementType())) in IsStructurallyEquivalent()
823 const auto *Vec2 = cast<DependentVectorType>(T2); in IsStructurallyEquivalent() local
824 if (Vec1->getVectorKind() != Vec2->getVectorKind()) in IsStructurallyEquivalent()
827 Vec2->getSizeExpr())) in IsStructurallyEquivalent()
830 Vec2->getElementType())) in IsStructurallyEquivalent()
838 const auto *Vec2 = cast<VectorType>(T2); in IsStructurallyEquivalent() local
840 Vec2->getElementType())) in IsStructurallyEquivalent()
842 if (Vec1->getNumElements() != Vec2->getNumElements()) in IsStructurallyEquivalent()
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| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/ |
| H A D | bitcast-inseltpoison.ll | 433 define i64 @Vec2(i64 %in) {
434 ; CHECK-LABEL: @Vec2(
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| H A D | bitcast.ll | 551 define i64 @Vec2(i64 %in) {
552 ; CHECK-LABEL: @Vec2(
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrMMA.td | 607 dag Vec2 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx0));
623 Extracts.Vec2>;
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1872 SDValue Vec2; in ExpandBVWithShuffles() local
1874 Vec2 = IntermedVals[1].first; in ExpandBVWithShuffles()
1876 Vec2 = DAG.getUNDEF(VT); in ExpandBVWithShuffles()
1885 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec); in ExpandBVWithShuffles()
1987 SDValue Vec2; in ExpandBUILD_VECTOR() local
1989 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); in ExpandBUILD_VECTOR()
1991 Vec2 = DAG.getUNDEF(VT); in ExpandBUILD_VECTOR()
1994 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec); in ExpandBUILD_VECTOR()
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| /llvm-project-15.0.7/llvm/test/Bindings/OCaml/ |
| H A D | core.ml | 1076 …* CHECK: %build_shufflevector = shufflevector <4 x i32> %Vec1, <4 x i32> %Vec2, <4 x i32> <i32 1, …
1118 let vec2 = build_insertelement t2 p1 p2 "Vec2" atentry in
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| /llvm-project-15.0.7/llvm/lib/Bitcode/Reader/ |
| H A D | BitcodeReader.cpp | 5012 Value *Vec1, *Vec2, *Mask; in parseFunctionBody() local
5017 Vec2, CurBB)) in parseFunctionBody()
5023 if (!Vec1->getType()->isVectorTy() || !Vec2->getType()->isVectorTy()) in parseFunctionBody()
5026 I = new ShuffleVectorInst(Vec1, Vec2, Mask); in parseFunctionBody()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 361 Value *Vec2 = nullptr; in isFixedVectorShuffle() local
393 } else if (!Vec2 || Vec2 == Vec) { in isFixedVectorShuffle()
394 Vec2 = Vec; in isFixedVectorShuffle()
410 if (CommonShuffleMode == Select && Vec2) in isFixedVectorShuffle()
414 return Vec2 ? TargetTransformInfo::SK_PermuteTwoSrc in isFixedVectorShuffle()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 11226 SDValue Vec2 = Op2.getOperand(0); in performFMACombine() local
11251 if (Vec1 == Vec2 || Vec3 == Vec4) in performFMACombine()
11254 if (Vec1.getValueType() != MVT::v2f16 || Vec2.getValueType() != MVT::v2f16) in performFMACombine()
11257 if ((Vec1 == Vec3 && Vec2 == Vec4) || in performFMACombine()
11258 (Vec1 == Vec4 && Vec2 == Vec3)) { in performFMACombine()
11259 return DAG.getNode(AMDGPUISD::FDOT2, SL, MVT::f32, Vec1, Vec2, FMAAcc, in performFMACombine()
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | ProgrammersManual.rst | 1746 PackedVector<State, 2> Vec2;
1747 Vec2.push_back(SecondCondition);
1749 Vec1 |= Vec2;
|