Searched refs:ValOp (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2692 const MachineOperand &ValOp = MI.getOperand(TakeOp); in evaluateHexCondMove() local
2696 if (ValOp.isImm()) { in evaluateHexCondMove()
2697 int64_t V = ValOp.getImm(); in evaluateHexCondMove()
2705 if (ValOp.isReg()) { in evaluateHexCondMove()
2706 RegisterSubReg R(ValOp); in evaluateHexCondMove()
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| H A D | HexagonSplitDouble.cpp | 638 MachineOperand &ValOp = Load ? MI->getOperand(0) in splitMemRef() local
641 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg()); in splitMemRef()
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| H A D | HexagonBitSimplify.cpp | 1954 MachineOperand &ValOp = MI->getOperand(2); in genStoreUpperHalf() local
1955 BitTracker::RegisterRef RS = ValOp; in genStoreUpperHalf()
1965 ValOp.setReg(H.Reg); in genStoreUpperHalf()
1966 ValOp.setSubReg(H.Sub); in genStoreUpperHalf()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | SROA.cpp | 793 Value *ValOp = SI.getValueOperand(); in visitStoreInst() local
794 if (ValOp == *U) in visitStoreInst()
803 if (isa<ScalableVectorType>(ValOp->getType())) in visitStoreInst()
806 uint64_t Size = DL.getTypeStoreSize(ValOp->getType()).getFixedSize(); in visitStoreInst()
824 assert((!SI.isSimple() || ValOp->getType()->isSingleValueType()) && in visitStoreInst()
826 handleLoadOrStore(ValOp->getType(), SI, Offset, Size, SI.isVolatile()); in visitStoreInst()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 6562 SDValue ValOp = GetWidenedVector(ST->getValue()); in GenWidenVectorStores() local
6567 EVT ValVT = ValOp.getValueType(); in GenWidenVectorStores()
6611 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, in GenWidenVectorStores()
6625 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); in GenWidenVectorStores()
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