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Searched refs:VZIP (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Daarch64-vuzp.ll62 ; Check that this pattern is recognized as a VZIP and
H A Darm64-zip.ll81 ; Undef shuffle indices should not prevent matching to VZIP:
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvzip.ll68 ; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
202 ; Undef shuffle indices should not prevent matching to VZIP:
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h207 VZIP, // zip (interleave) enumerator
H A DARMScheduleR52.td830 def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "VSWP", "VTRN", "VUZP", "VZIP")…
H A DARMScheduleSwift.td600 (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
H A DARMISelLowering.cpp1765 MAKE_CASE(ARMISD::VZIP) in getTargetNodeName()
7461 return ARMISD::VZIP; in isNEONTwoResultShuffleMask()
7469 return ARMISD::VZIP; in isNEONTwoResultShuffleMask()
8399 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
H A DARMISelDAGToDAG.cpp4252 case ARMISD::VZIP: { in Select()
H A DARMInstrNEON.td525 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
2606 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
7145 // VZIP : Vector Zip (Interleave)
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_neon.td668 def VZIP : WInst<"vzip", "2..", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;