Searched refs:VUZP (Results 1 – 9 of 9) sorted by relevance
| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-uzp.ll | 81 ; Undef shuffle indices should not prevent matching to VUZP:
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| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | vuzp.ll | 68 ; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors. 202 ; Undef shuffle indices should not prevent matching to VUZP:
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 208 VUZP, // unzip (deinterleave) enumerator
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| H A D | ARMScheduleR52.td | 830 def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "VSWP", "VTRN", "VUZP", "VZIP")…
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| H A D | ARMScheduleSwift.td | 600 (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
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| H A D | ARMISelLowering.cpp | 1766 MAKE_CASE(ARMISD::VUZP) in getTargetNodeName() 7459 return ARMISD::VUZP; in isNEONTwoResultShuffleMask() 7467 return ARMISD::VUZP; in isNEONTwoResultShuffleMask() 8395 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle() 12392 if (N->getOpcode() == ARMISD::VUZP) in IsVUZPShuffleNode()
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| H A D | ARMISelDAGToDAG.cpp | 4275 case ARMISD::VUZP: { in Select()
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| H A D | ARMInstrNEON.td | 526 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>; 2606 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register. 7133 // VUZP : Vector Unzip (Deinterleave)
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| /llvm-project-15.0.7/clang/include/clang/Basic/ |
| H A D | arm_neon.td | 669 def VUZP : WInst<"vuzp", "2..", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
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