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Searched refs:VT4 (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-transforms.mlir342 // CHECK: %[[VT4:.*]] = vector.transfer_read %[[ARG1]][%[[C0]], %[[C0]]], {{.*}} : memref<4…
346 // CHECK: %[[CMP0:.*]] = arith.cmpf ult, %[[VT0]], %[[VT4]] : vector<2x2xf32>
354 // CHECK: %[[VT4:.*]] = vector.transfer_read %[[ARG1]][%[[C0]], %[[C0]]], {{.*}} : memref<4…
358 // CHECK: %[[SEL0:.*]] = arith.select %[[CMP0]], %[[VT0]], %[[VT4]] : vector<2x2xi1>, vecto…
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrNEON.td6456 multiclass ExtractEltEvenF16<ValueType VT4, ValueType VT8> {
6457 def : Pat<(extractelt (VT4 DPR:$src), imm_even:$lane),
6459 (v2f32 (COPY_TO_REGCLASS (VT4 DPR:$src), DPR_VFP2)),
6467 multiclass ExtractEltOddF16VMOVH<ValueType VT4, ValueType VT8> {
6468 def : Pat<(extractelt (VT4 DPR:$src), imm_odd:$lane),
6471 (v2f32 (COPY_TO_REGCLASS (VT4 DPR:$src), DPR_VFP2)),
6544 multiclass InsertEltF16<ValueType VTScalar, ValueType VT4, ValueType VT8> {
6545 def : Pat<(insertelt (VT4 DPR:$src1), (VTScalar HPR:$src2), imm:$lane),
6546 (VT4 (VSETLNi16 DPR:$src1,
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h620 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp9256 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4) { in getVTList() argument
9262 ID.AddInteger(VT4.getRawBits()); in getVTList()
9271 Array[3] = VT4; in getVTList()