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Searched refs:VSRL (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/VE/VELIntrinsics/
H A Dvsrl.ll6 ;;; We test VSRL*vvl, VSRL*vvl_v, VSRL*vrl, VSRL*vrl_v, VSRL*vil, VSRL*vil_v,
7 ;;; VSRL*vvml_v, VSRL*vrml_v, VSRL*viml_v, PVSRL*vvl, PVSRL*vvl_v, PVSRL*vrl,
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h408 X86_INTRINSIC_DATA(avx2_psrl_d, INTR_TYPE_2OP, X86ISD::VSRL, 0),
409 X86_INTRINSIC_DATA(avx2_psrl_q, INTR_TYPE_2OP, X86ISD::VSRL, 0),
410 X86_INTRINSIC_DATA(avx2_psrl_w, INTR_TYPE_2OP, X86ISD::VSRL, 0),
874 X86_INTRINSIC_DATA(avx512_psrl_d_512, INTR_TYPE_2OP, X86ISD::VSRL, 0),
875 X86_INTRINSIC_DATA(avx512_psrl_q_512, INTR_TYPE_2OP, X86ISD::VSRL, 0),
876 X86_INTRINSIC_DATA(avx512_psrl_w_512, INTR_TYPE_2OP, X86ISD::VSRL, 0),
1302 X86_INTRINSIC_DATA(sse2_psrl_d, INTR_TYPE_2OP, X86ISD::VSRL, 0),
1303 X86_INTRINSIC_DATA(sse2_psrl_q, INTR_TYPE_2OP, X86ISD::VSRL, 0),
1304 X86_INTRINSIC_DATA(sse2_psrl_w, INTR_TYPE_2OP, X86ISD::VSRL, 0),
H A DX86ISelLowering.h353 VSRL, enumerator
H A DX86InstrFragmentsSIMD.td235 def X86vsrl : SDNode<"X86ISD::VSRL", X86vshiftuniform>;
H A DX86ISelLowering.cpp26153 case X86ISD::VSRL: in getTargetVShiftUniformOpcode()
26155 return IsVariable ? X86ISD::VSRL : X86ISD::VSRLI; in getTargetVShiftUniformOpcode()
33565 NODE_NAME_CASE(VSRL) in getTargetNodeName()
40980 case X86ISD::VSRL: in SimplifyDemandedVectorEltsForTargetNode()
40991 return (UseOpc == X86ISD::VSHL || UseOpc == X86ISD::VSRL || in SimplifyDemandedVectorEltsForTargetNode()
41429 case X86ISD::VSRL: in SimplifyDemandedVectorEltsForTargetNode()
47060 X86ISD::VSRL == N->getOpcode()) && in combineVectorShiftVar()
54047 case X86ISD::VSRL: in combineConcatVectorOps()
55121 case X86ISD::VSRL: in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td76 // VSRL - One of the 32 128-bit VSX registers that overlap with the scalar
78 class VSRL<FPR SubReg, string n> : PPCReg<n> {
155 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>,
169 … [!cast<VSRL>("VSL"#Index), !cast<VSRL>("VSL"#!add(Index, 1))]>,
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPInstrPatternsVec.td385 i64, v256i64, "VSRL",
H A DVEInstrVec.td610 // e.g. VSLL, VSRL, VSLA, and etc.
1058 // Section 8.12.3 - VSRL (Vector Shift Right Logical)
1059 let cx = 0, cx2 = 0 in defm VSRL : RVSm<"vsrl", 0xf5, I64, V64, VM>;
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrVector.td822 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>;
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-intrinsics-01.ll1546 ; VSRL.