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Searched refs:VRs (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dfp-move-13.ll21 ; Test 128-bit moves from GPRs to VRs. i128 isn't a legitimate type,
34 ; Test 128-bit moves from VRs to GPRs, with the same restriction as f2.
H A Dvec-args-07.ll7 ; Up to eight vector return values fit into VRs.
H A Dvec-args-06.ll7 ; Up to eight vector return values fit into VRs.
H A Dzos-prologue-epilog.ll80 ; Spill all FPRs and VRs
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dwrong-stack-slot-rv64.mir6 # vector registers (VRs). If this test changes, make sure there is no overlap
7 # between slots for GPRs and VRs.
H A Dwrong-stack-slot-rv32.mir6 # vector registers (VRs). If this test changes, make sure there is no overlap
7 # between slots for GPRs and VRs.
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp626 SortableVectorType VRs; in buildOrderingBT() local
628 VRs.push_back(I.first); in buildOrderingBT()
629 llvm::sort(VRs, LexCmp); in buildOrderingBT()
631 for (unsigned i = 0, n = VRs.size(); i < n; ++i) in buildOrderingBT()
632 RO.insert(std::make_pair(VRs[i], i)); in buildOrderingBT()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td208 // Even though 3 GPRs, 4 FPRs, and 8 VRs may be used,
212 // and VRs respectively, but if a FP value or vector argument occupies one of