Home
last modified time | relevance | path

Searched refs:VRegInfo (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/MIRParser/
H A DMIParser.h37 struct VRegInfo { struct
173 DenseMap<Register, VRegInfo *> VRegInfos;
174 StringMap<VRegInfo *> VRegInfosNamed;
187 VRegInfo &getVRegInfo(Register Num);
188 VRegInfo &getVRegInfoNamed(StringRef RegName);
232 VRegInfo *&Info, StringRef Src,
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp46 struct VRegInfo { struct
99 const VRegInfo &RegInfo) const;
113 VRegInfo *VRegInfos;
201 VRegInfo &MORegInfo = VRegInfos[MORegIdx]; in addUsedLanesOnOperand()
294 VRegInfo &RegInfo = VRegInfos[DefRegIdx]; in transferDefinedLanesStep()
474 const VRegInfo &DefRegInfo = VRegInfos[DefRegIdx]; in isUndefInput()
494 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
504 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
520 const VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
540 const VRegInfo &RegInfo = VRegInfos[RegIdx]; in runOnce()
[all …]
H A DMachineRegisterInfo.cpp47 VRegInfo.reserve(256); in MachineRegisterInfo()
58 VRegInfo[Reg].first = RC; in setRegClass()
63 VRegInfo[Reg].first = &RegBank; in setRegBank()
146 VRegInfo.grow(Reg); in createIncompleteVirtualRegister()
164 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
173 VRegInfo[Reg].first = VRegInfo[VReg].first; in cloneVirtualRegister()
190 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr); in createGenericVirtualRegister()
204 if (!VRegInfo[Reg].second) in clearVirtRegs()
210 VRegInfo.clear(); in clearVirtRegs()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h74 VRegInfo; variable
110 return VRegInfo[RegNo.id()].second; in getRegUseDefListHead()
116 return VRegInfo[RegNo.id()].second; in getRegUseDefListHead()
643 assert(VRegInfo[Reg.id()].first.is<const TargetRegisterClass *>() && in getRegClass()
645 return VRegInfo[Reg.id()].first.get<const TargetRegisterClass *>(); in getRegClass()
660 const RegClassOrRegBank &Val = VRegInfo[Reg].first; in getRegClassOrNull()
669 const RegClassOrRegBank &Val = VRegInfo[Reg].first; in getRegBankOrNull()
677 return VRegInfo[Reg].first; in getRegClassOrRegBank()
688 VRegInfo[Reg].first = RCOrRB; in setRegClassOrRegBank()
765 unsigned getNumVirtRegs() const { return VRegInfo.size(); } in getNumVirtRegs()
/llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp325 VRegInfo *Info = new (Allocator) VRegInfo; in getVRegInfo()
337 VRegInfo *Info = new (Allocator) VRegInfo; in getVRegInfoNamed()
446 bool parseRegister(Register &Reg, VRegInfo *&VRegInfo);
1169 VRegInfo *Info; in parseStandaloneRegister()
1498 case VRegInfo::NORMAL: in parseRegisterClassOrBank()
1527 case VRegInfo::UNKNOWN: in parseRegisterClassOrBank()
1528 case VRegInfo::GENERIC: in parseRegisterClassOrBank()
1529 case VRegInfo::REGBANK: in parseRegisterClassOrBank()
1530 RegInfo.Kind = RegBank ? VRegInfo::REGBANK : VRegInfo::GENERIC; in parseRegisterClassOrBank()
1537 case VRegInfo::NORMAL: in parseRegisterClassOrBank()
[all …]
H A DMIRParser.cpp596 Info.Kind = VRegInfo::GENERIC; in parseRegisterInfo()
601 Info.Kind = VRegInfo::NORMAL; in parseRegisterInfo()
610 Info.Kind = VRegInfo::REGBANK; in parseRegisterInfo()
616 if (Info.Kind != VRegInfo::NORMAL) in parseRegisterInfo()
633 VRegInfo *Info; in parseRegisterInfo()
667 case VRegInfo::UNKNOWN: in setupRegisterInfo()
672 case VRegInfo::NORMAL: in setupRegisterInfo()
677 case VRegInfo::GENERIC: in setupRegisterInfo()
679 case VRegInfo::REGBANK: in setupRegisterInfo()
686 const VRegInfo &Info = *P.second; in setupRegisterInfo()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/Mips/
H A DsetRegClassOrRegBank.ll6 ; which sets RegClassOrRegBank in VRegInfo.