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Searched refs:VReg0 (Results 1 – 1 of 1) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp240 Register VReg0 = MIB.getReg(0); in selectMergeValues() local
241 (void)VReg0; in selectMergeValues()
242 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues()
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
272 Register VReg0 = MIB.getReg(0); in selectUnmergeValues() local
273 (void)VReg0; in selectUnmergeValues()
274 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues()
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()