| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | VOPCInstructions.td | 44 // VOPC classes
47 // VOPC instructions are a special case because for the 32-bit
62 // VOPC DPP Instructions do not need an old operand
125 let VOPC = 1;
137 let VOPC = 1;
290 let VOPC = 1;
352 let VOPC = 1;
791 let VOPC = 1;
838 let VOPC = 1;
1044 let VOPC = 1;
[all …]
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| H A D | SIInstrFormats.td | 30 field bit VOPC = 0;
165 let TSFlags{9} = VOPC;
237 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
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| H A D | SIInstrInfo.td | 1605 SDWAVopcDst, // VOPC
2045 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
2063 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
2086 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
2152 ""); // use $sdst for VOPC
2180 ""); // use $sdst for VOPC
2224 " vcc", // use vcc token as dst for VOPC instructions
2241 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
2253 "$sdst", // VOPC
2269 … " $src0_sel $src1_sel", // No dst_sel, dst_unused and output modifiers for VOPC
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| H A D | SIDefines.h | 42 VOPC = 1 << 9, enumerator
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| H A D | SIInstrInfo.h | 456 return MI.getDesc().TSFlags & SIInstrFlags::VOPC; in isVOPC()
460 return get(Opcode).TSFlags & SIInstrFlags::VOPC; in isVOPC()
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| H A D | SISchedule.td | 69 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
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| H A D | AMDGPU.td | 427 "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
439 "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
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| H A D | VOPInstructions.td | 497 // 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | AMDGPUInstructionSyntax.rst | 144 Most *VOP1*, *VOP2* and *VOPC* instructions have several variants:
153 *VOP1*, *VOP2* and *VOPC* (32-bit) encoding _e32
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| H A D | AMDGPUUsage.rst | 14486 For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
14490 * _e32 for 32-bit VOP1/VOP2/VOPC
14495 VOP1/VOP2/VOP3/VOPC examples:
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| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | vopc_dpp.mir | 94 ; Do not combine VOPC when row_mask or bank_mask is not 0xf
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 631 (Desc.TSFlags & SIInstrFlags::VOPC) && in needsImpliedVcc()
648 (Desc.TSFlags & SIInstrFlags::VOPC) && in printOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 498 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) in getInstruction()
796 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || in convertDPP8Inst()
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/ |
| H A D | sdwa_gfx9.txt | 406 # VOPC
511 # VOPC with arbitrary SGPR destination
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3426 (SIInstrFlags::VOPC | in validateConstantBusLimitations()
4012 const auto Enc = VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA; in validateLdsDirect()
8999 cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI()); in cvtSdwaVOPC()
9032 } else if (BasicInstType == SIInstrFlags::VOPC && in cvtSDWA()
9090 case SIInstrFlags::VOPC: in cvtSDWA()
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| /llvm-project-15.0.7/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX7.rst | 1145 VOPC section in Instructions
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| H A D | AMDGPUAsmGFX8.rst | 1427 VOPC section in Instructions
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| H A D | AMDGPUAsmGFX90a.rst | 1649 VOPC section in Instructions
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| H A D | AMDGPUAsmGFX9.rst | 1686 VOPC section in Instructions
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| H A D | AMDGPUAsmGFX10.rst | 1956 VOPC section in Instructions
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| H A D | AMDGPUAsmGFX1030.rst | 1869 VOPC section in Instructions
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| H A D | AMDGPUAsmGFX940.rst | 1668 VOPC section in Instructions
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